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cy8c24094, cy8c24794 cy8c24894, cy8c24994 psoc ? programmable system-on-chip cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-12018 rev. *v revised may 27, 2010 1. features xres pin to support in-system serial programming (issp) and external reset control in cy8c24894 powerful harvard-architecture processor ? m8c processor speeds to 24 mhz ? two 8 8 multiply, 32-bit accumulate ? low power at high speed ? 3 v to 5.25 v operating voltage ? industrial temperature range: ?40 c to +85 c ? usb temperature range: ?10 c to +85 c advanced peripherals (psoc ? blocks) ? six rail-to-rail analog psoc blocks provide: ? up to 14-bit analog-to-digital converters (adcs) ? up to 9-bit digital-to-analog converters (dacs) ? programmable gain amplifiers (pgas) ? programmable filters and comparators ? four digital psoc blocks provide: ? 8 to 32-bit timers, counters , and pulse width modulators (pwms) ? cyclical redundancy check (crc) and pseudo random sequence (prs) modules ? full-duplex universal asynchro nous receiver transmitter (uart) ? multiple serial peripheral interface (spi) masters or slaves ? connectable to all general purpose i/o (gpio) pins ? complex peripherals by combining blocks ? capacitive sensing application (csa) capability full-speed usb (12 mbps) ? four unidirectional endpoints ? one bidirectional control endpoint ? usb 2.0 compliant ? dedicated 256 byte buffer ? no external crystal required flexible on-chip memory ? 16 kb flash program storage 50,000 erase and write cycles ? 1 kb static random access memory (sram) data storage ? issp ? partial flash updates ? flexible protection modes ? electrically erasable programmable read-only memory (eeprom) emulation in flash programmable pin configurations ? 25 ma sink, 10 ma source on all gpios ? pull-up, pull-down, high z, strong, or open drain drive modes on all gpios ? up to 48 analog inputs on gpio ? two 33 ma analog outputs on gpio ? configurable interrupt on all gpios precision, programmable clocking ? internal 4% 24- and 48- mhz oscillator ? internal oscillator for watchdog and sleep ? 0.25% accuracy for usb with no external components additional system resources ? i 2 c slave, master, and multi-master to 400 khz ? watchdog and sleep timers ? user-configurable low-voltage detection (lvd) digital system sram 1k interrupt controller sleep and watchdog clock sources (includes imo and ilo) global digital interconnect global analog interconnect psoc core cpu core (m8c) srom flash 16 kb digital block array digital clocks system resources analog system analog ref. port 5 port 4 port 3 port 2 port 1 port 0 analog drivers analog block array internal voltage ref. por and lvd system resets 2 macs decimator type 2 i 2 c usb port 7 s y s t e m b u s analog input muxing 2. logic block diagram [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 2 of 51 3. contents features............................................................................... 1 logic block diagram.......................................................... 1 contents .............................................................................. 2 psoc functional overview................................................ 3 the psoc core ............................................................. 3 the digital system ........................................................ 3 the analog system ....................................................... 4 additional system resources . ...................................... 5 psoc device characteristics .. ...................................... 5 getting started.................................................................... 5 application notes .......................................................... 5 development kits .......................................................... 5 training ......................................................................... 5 cypros consultants ...................................................... 5 solutions library............................................................ 5 technical support ......................................................... 5 development tools ............................................................ 6 psoc designer software subsyst ems............. ............. 6 designing with psoc designer ......................................... 7 select user modules ..................................................... 7 configure user modules.......... ...................................... 7 organize and connect ............... .............. .............. ....... 7 generate, verify, and debug......................................... 7 pin information ................................................................... 8 56-pin part pinout ......................................................... 8 56-pin part pinout (with xres) ..................................... 9 68-pin part pinout ....................................................... 10 68-pin part pinout (on-chip debug)........................... 11 100-ball vfbga part pinout ....................................... 12 100-ball vfbga part pinout (on-chip debug)........... 14 100-pin part pinout (on-chip debug)......................... 16 register reference................... ........................................ 18 register conventions .................................................. 18 register mapping tables ......... ............... .............. ...... 18 register map bank 0 table: user space .................... 19 register map bank 1 table: configuration space ...... 20 electrical specifications .................................................. 21 absolute maximum ra tings......................................... 22 operating temperature ............................................... 22 dc electrical characteristics. ...................................... 23 ac electrical characteristics . ...................................... 31 packaging dimensions .................................................... 39 thermal impedance .................................................... 43 solder reflow peak temperat ure ............................... 43 development tool selection ...... .............. .............. ......... 44 software ...................................................................... 44 development kits ........................................................ 44 evaluation tools.......................................................... 44 device programmers................ ................................... 45 accessories (emulation and programming) ................ 45 ordering information........................................................ 46 ordering code definitions ...... ..................................... 47 document conventions ................................................... 48 acronyms used ........................................................... 48 units of measure ......................................................... 48 numeric naming..................... ..................................... 48 document history page ................................................... 49 sales, solutions, and legal information ........................ 51 [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 3 of 51 4. psoc functional overview the psoc family consists of many devices with on-chip controllers. these devices are designed to replace multiple traditional mcu-based system components with one low-cost single-chip programmable component. a psoc device includes configurable blocks of analog and digital logic, and programmable interconnect. this architecture makes it possible for you to create customized peri pheral configurations, to match the requirements of each individua l application. additionally, a fast central processing unit (cpu), flash program memory, sram data memory, and configurable i/o are included in a range of convenient pinouts. the psoc architecture, shown in ?? on page 1, consists of four main areas: the core , the system resources, the digital system, and the analog syst em. configurable globa l bus resources allow combining all of the device resources into a complete custom system. each cy8c24x94 psoc de vice includes four digital blocks and four analog blo cks. depending on the psoc package, up to 28 gpios are also included. the gpios provide access to the global digital and analog interconnects. 4.1 the psoc core the psoc core is a powerful engine that supports a rich instruction set. it encompasses sram for data storage, an interrupt controller, sleep and watchdog timers, and internal main oscillator (imo) and internal low s peed oscillator (ilo). the cpu core, called the m8c, is a powerful processor with speeds up to 24 mhz. the m8c is a four-million instructions per second (mips) 8-bit harvard-architecture microprocessor. system resources provide these additional capabilities: digital clocks for increased flexibility i 2 c functionality to implement an i 2 c master and slave an internal voltage reference, multi-master, that provides an absolute value of 1.3 v to a number of psoc subsystems a switch mode pump (smp) that generates normal operating voltages from a single battery cell various system resets supported by the m8c the digital system consists of an array of digital psoc blocks that may be configured into any number of digital peripherals. the digital blocks are connected to the gpios through a series of global buses. these can route any signal to any pin, freeing designs from the constraints of a fixed peripheral controller. the analog system consists of four analog psoc blocks, supporting comparators, and anal og-to-digital conversion up to 10 bits of precision. 4.2 the digital system the digital system consists of four digital psoc blocks. each block is an 8-bit resource that is used alone or combined with other blocks to form 8-, 16-, 24-, and 32-bit peripherals, which are called user modules. digital peripheral configurations include: pwms (8- to 32-bit) pwms with dead band (8- to 32-bit) counters (8- to 32-bit) timers (8- to 32-bit) uart 8-bit with selectable parity spi master and slave i 2 c slave and multi-master crc/generator (8-bit) irda prs generators (8- to 32-bit) the digital blocks are connected to any gpio through a series of global buses that can route any signal to any pin. the buses also allow for signal multiplexing and for performing logic operations. this configurability frees your designs from the constraints of a fixed peripheral controller. digital blocks are provided in ro ws of four, where the number of blocks varies by psoc device fa mily. this allows the optimum choice of system resources fo r your application. family resources are shown in table 4-1 on page 5. figure 4-1. digital system block diagram digital system to system bus d i g i t a l c l o c k s f r o m c o r e digital psoc block array to analog system 8 row input configuration row output configuration 8 8 8 row 0 dbb00 dbb01 dcb02 dcb03 4 4 gie[7:0] gio[7:0] goe[7:0] goo[7:0] global digital interconnect port 1 port 0 port 3 port 2 port 5 port 4 port 7 [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 4 of 51 4.3 the analog system the analog system is composed of six configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. analog peripherals are very flexible and can be customized to support spec ific application requirements. some of the more common psoc analog functions (most available as user modules) are as follows. adcs (up to two, with 6- to 14-bit resolution, selectable as incremental, delta sigma, and sar) filters (2 and 4 pole band-pass, low-pass, and notch) amplifiers (up to two, with selectable gain to 48x) instrumentation amplifiers (one with selectable gain to 93x) comparators (up to two, with 16 selectable thresholds) dacs (up to two, with 6- to 9-bit resolution) multiplying dacs (up to two, with 6- to 9-bit resolution) high current output drivers (two with 30 ma drive as a psoc core resource) 1.3-v reference (as a system resource) dtmf dialer modulators correlators peak detectors many other topologies possible analog blocks are arranged in a co lumn of three, which includes one continuous time (ct) and two switched capacitor (sc) blocks, as shown in figure 4-2. figure 4-2. analog system block diagram 4.3.1 the analog multiplexer system the analog mux bus can connect to every gpio pin in ports 0-5. pins are connected to the bus individually or in any combination. the bus also connects to the analog system fo r analysis with comparators and analog-to-digital c onverters. it is split into two sections for simultaneous dual-channel processing. an additional 8:1 analog input multiplexer provides a second path to bring port 0 pins to the analog array. switch-control logic enables selected pins to precharge continu- ously under hardware control. this enables capacitive measurement for applications su ch as touch sensing. other multiplexer applications include: track pad, finger sensing chip-wide mux that enables analog input from up to 48 i/o pins crosspoint connection between any i/o pin combinations acb00 acb01 block array array input c on fig uratio n aci1[1:0] asd20 aci0[1:0] p0[6] p0[4] p0[2] p0[0] p2[2] p2[0] p2[6] p2[4] refin agndin p0[7] p0[5] p0[3] p0[1] p2[3] p2[1] reference generators agndin r efin bandgap refhi reflo agnd asd11 asc21 asc10 interface to digital system m8c interface (address bus, data bus, etc.) analog reference a ll io (except port 7) analog mux bus [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 5 of 51 4.4 additional system resources system resources provide addi tional capability useful to complete systems. additional re sources include a multiplier, decimator, low-voltage detection, and power on reset. brief statements describing the merits of each resource follow. full-speed usb (12 mbps) with five configurable endpoints and 256 bytes of ram. no external components required except for two series resistors. wider than commercial temperature usb operation ?10c to +85c). digital clock dividers provide three customizable clock frequencies for use in applications. the clocks can be routed to both the digital and analog systems. additional clocks are generated using digital psoc blocks as clock dividers. two multiply accumulates (macs) provide fast 8-bit multipliers with 32-bit accumulate, to assist in both general math and digital filters. decimator provides a custom har dware filter for digital signal processing applications including creation of delta sigma adcs. the i 2 c module provides 100- and 400-khz communication over two wires. slave, master, multi-master are supported. low voltage detection interrupts signal the application of falling voltage levels, while the advanced power-on reset (por) circuit eliminates the need for a system supervisor. an internal 1.3-v reference provides an absolute reference for the analog system, includ ing adcs and dacs. versatile analog multiplexer system. 4.5 psoc device characteristics depending on your psoc device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4 analog blocks. the following tabl e lists the resources available for specific psoc device groups. the device covered by this data sheet is shown in the highlighted row of the table 5. getting started for in-depth information, along with detailed programming infor- mation, see the technical reference manual for this psoc device. for up-to-date ordering, packaging, and electrical specification information, see the latest pso c device data sheets on the web at http://www.cypress.com . 5.1 application notes cypress application notes are an excellent introduction to the wide variety of possi ble psoc designs. 5.2 development kits psoc development kits are available online from and through a growing number of regional and global distributors, which include arrow, avnet, digi-key, farnell, future electronics, and newark. 5.3 training free psoc technical training (on demand, webinars, and workshops), which is available online via www.cypress.com , covers a wide variety of topics an d skill levels to assist you in your designs. 5.4 cypros consultants certified psoc consultants offer everything from technical assistance to completed psoc designs. to contact or become a psoc consultant go to the cypros consultants web site. 5.5 solutions library visit our growing library of solution focused designs . here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. 5.6 technical support technical support ? including a searchable knowledge base articles and technical forums ? is also available online. if you cannot find an answer to your question, call our technical support hotline at 1-800-541-4736. table 4-1. psoc device characteristics psoc part number digital i/o digital rows digital blocks analog inputs analog outputs analog columns analog blocks sram size flash size cy8c29x66 up to 64 4 16 12 4 4 12 2 kb 32 kb cy8c27x43 up to 44 2 8 12 4 4 12 256 bytes 16 kb cy8c24x94 56 1 4 48 2 2 6 1 kb 16 kb cy8c24x23a up to 24 1 4 12 2 2 6 256 bytes 4 kb cy8c21x34 up to 28 1 4 28 0 2 4 512 bytes 8 kb cy8c21x23 16 1 4 8 0 2 4 256 bytes 4 kb cy8c20x34 up to 28 0 0 28 0 0 3 512 bytes 8 kb [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 6 of 51 6. development tools psoc designer? is the revolutionary integrated design environment (ide) that you can use to customize psoc to meet your specific application requirements. psoc designer software accelerates system design and ti me to market. develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. then, customize your design by leveraging the dynamically generated application programming interface (api) libraries of code. finally, debug and test your designs with the integrated debug environment, including in-circuit emulation and standard software debug features. psoc designer includes: application editor graphical user interface (gui) for device and user module configuration and dynamic reconfiguration extensive user module catalog integrated source-code editor (c and assembly) free c compiler with no size restrictions or time limits built-in debugger in-circuit emulation built-in support for communication interfaces: ? hardware and software i 2 c slaves and masters ? full-speed usb 2.0 ? up to four full-duplex universal asynchronous receiver/trans- mitters (uarts), spi master and slave, and wireless psoc designer supports the entire library of psoc 1 devices and runs on windows xp, windows vista, and windows 7. 6.1 psoc designer software subsystems 6.1.1 design entry in the chip-level view, choose a base device to work with. then select different onboard analog and digital components that use the psoc blocks, which are called user modules. examples of user modules are analog-to-digital converters (adcs), digital-to-analog converters (dacs), amplifiers, and filters. configure the user modules for your chosen application and connect them to each other and to the proper pins. then generate your project. this prepopulates your project with apis and libraries that you can use to program your application. the tool also supports easy deve lopment of multiple configura- tions and dynamic reconfigurat ion. dynamic reconfiguration makes it possible to change configurations at run time. in essence, this allows you to use more than 100 percent of psoc's resources for a given application. 6.1.2 code generation tools the code generation tools work seamlessly within the psoc designer interface and have been tested with a full range of debugging tools. you can develop your design in c, assembly, or a combination of the two. assemblers . the assemblers allow you to merge assembly code seamlessly with c code. link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. c language compilers . c language compilers are available that support the psoc family of devices. the products allow you to create complete c programs fo r the psoc family devices. the optimizing c compilers provide all of the features of c, tailored to the psoc architecture. they come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. 6.1.3 debugger psoc designer has a debug environment that provides hardware in-circuit emulation, al lowing you to test the program in a physical system while providing an internal view of the psoc device. debugger commands allow you to read and program and read and write data memory, and read and write i/o registers. you can read and write cpu regist ers, set and clear breakpoints, and provide program run, halt , and step control. the debugger also allows you to create a trace buffer of registers and memory locations of interest. 6.1.4 online help system the online help system displays online, context-sensitive help. designed for procedural and quick reference, each functional subsystem has its own context-se nsitive help. th is system also provides tutorials and links to faqs and an online support forum to aid the designer. 6.1.5 in-circuit emulator a low-cost, high-functionality in-circuit emulator (ice) is available for development support. this hardware can program single devices. the emulator consists of a ba se unit that connects to the pc using a usb port. the base unit is universal and operates with all psoc devices. emulation p ods for each device family are available separately. the emulation pod takes the place of the psoc device in the target board and performs full-speed (24-mhz) operation. [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 7 of 51 7. designing wi th psoc designer the development process for the psoc? device differs from that of a traditional fixed function microprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays divi dends in managing specification change during development and by lowering inventory costs. these configurable resources, called psoc blocks, have the ability to implement a wide variety of user-selectable functions. the psoc development process is summarized in four steps: 1. select user modules . 2. configure user modules. 3. organize and connect. 4. generate, verify, and debug. 7.1 select user modules psoc designer provides a library of prebuilt, pretested hardware peripheral components called ?user modules.? user modules make selecting and implementing peripheral devices, both analog and digital, simple. 7.2 configure user modules each user module that you select establishes the basic register settings that implement the selected function. they also provide parameters and properties that allow you to tailor their precise configuration to your particular application. for example, a pulse width modulator (pwm) user module configures one or more digital psoc blocks, one for each 8 bits of resolution. the user module parameters permit you to establish the pulse width and duty cycle. configure the parameters and properties to corre- spond to your chosen application. enter values directly or by selecting values from drop-down menus. all the user modules are documented in datasheets that may be viewed directly in psoc designer or on the cypress website. these user module datasheets explain the internal operation of the user module and provide performance specifications. each datasheet describes the use of each user module parameter, and other information you may need to successfully implement your design. 7.3 organize and connect you build signal chains at the chip level by interconnecting user modules to each other and the i/o pins. you perform the selection, configuration, and ro uting so that you have complete control over all on-chip resources. 7.4 generate, verify, and debug when you are ready to test the hardware configuration or move on to developing code for the project, you perform the ?generate configuration files? step. this causes psoc designer to generate source code that automat ically configures the device to your specification and provides the software for the system. the generated code provides application programming interfaces (apis) with high-level functi ons to control and respond to hardware events at run time and interrupt service routines that you can adapt as needed. a complete code development environment allows you to develop and customize your applic ations in either c, assembly language, or both. the last step in the development process takes place inside psoc designer?s debugger (access by clicking the connect icon). psoc designer downloads the hex image to the ice where it runs at full speed. psoc designer debugging capabil- ities rival those of systems costing many times more. in addition to traditional single-step, run-to-breakpoint and watch-variable features, the debug interface provides a large trace buffer and allows you to define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 8 of 51 8. pin information this section describes, lists, and illustrates the cy8c24x 94 psoc device family pins and pinout configuration. the cy8c24x94 psoc devices are available in the following packages , all of which are shown on the following pages. every port p in (labeled with a ?p?) is capable of digital i/o. however, v ss , v dd , and xres are not capable of digital i/o. 8.1 56-pin part pinout notes 1. this part cannot be programmed with reset mode; use power cycle mode when programming. 2. these are the issp pins, which are not high z at por. see the psoc technical reference manual for details. table 8-1. 56-pin part pinout (qfn [4] ) see legend details and footnotes in table 8-2 on page 9 . pin no. type name description figure 8-1. cy8c24794 56-pin psoc device [1] digital analog 1 i/o i, m p2[3] direct switched capacitor block input 2 i/o i, m p2[1] direct switched capacitor block input 3 i/o m p4[7] 4 i/o m p4[5] 5 i/o m p4[3] 6 i/o m p4[1] 7 i/o m p3[7] 8 i/o m p3[5] 9 i/o m p3[3] 10 i/o m p3[1] 11 i/o m p5[7] 12 i/o m p5[5] 13 i/o m p5[3] 14 i/o m p5[1] 15 i/o m p1[7] i 2 c serial clock (scl) 16 i/o m p1[5] i 2 c serial data (sda) 17 i/o m p1[3] 18 i/o m p1[1] i 2 c scl, issp sclk [3] 19 power v ss ground connection 20 usb d+ 21 usb d- 22 power v dd supply voltage 23 i/o p7[7] 24 i/o p7[0] 25 i/o m p1[0] i 2 c sda, issp sdata [3] 26 i/o m p1[2] 27 i/o m p1[4] optional external clock input (extclk) 28 i/o m p1[6] 29 i/o m p5[0] pin no. type name description 30 i/o m p5[2] digital analog 31 i/o m p5[4] 44 i/o m p2[6] external voltage reference (vref) input 32 i/o m p5[6] 45 i/o i, m p0[0] analog column mux input 33 i/o m p3[0] 46 i/o i, m p0[2] analog column mux input 34 i/o m p3[2] 47 i/o i, m p0[4] analog column mux input vref 35 i/o m p3[4] 48 i/o i, m p0[6] analog column mux input 36 i/o m p3[6] 49 power v dd supply voltage 37 i/o m p4[0] 50 power v ss ground connection 38 i/o m p4[2] 51 i/o i, m p0[7] analog column mux input 39 i/o m p4[4] 52 i/o i/o, m p0[5] analog column mux input and column output 40 i/o m p4[6] 53 i/o i/o, m p0[3] analog column mux input and column output 41 i/o i, m p2[0] direct switched capacitor block input 54 i/o i, m p0[1] analog column mux input 42 i/o i, m p2[2] direct switched capacitor block input 55 i/o m p2[7] 43 i/o m p2[4] external analog ground (agnd) input 56 i/o mp2[5] qfn (top view ) a, i, m, p2[3] a, i, m, p2[1] m, p4[7] m, p4[5] m, p4[3] m, p4[1] m, p3[7] m, p3[5] m, p3[3] m, p3[1] m, p5[7] m, p5[5] m, p5[3] m, p5[1] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 m, i2c scl, p1[7] m, i2c sda, p1[5] m, p1[3] m, i2c scl, p1[1] vss d+ d- vdd p7[7] p7[0] m, i2c sda, p1[0] m, p1[2] m, p1[4] m, p1[6] 15 16 17 18 19 20 21 22 23 24 25 26 27 28 p2[4], m p2[6], m p0[0], a, i, m p0[2], a, i, m p0[4], a, i, m p0[6], a, i, m vdd vss p0[7], a, i, m p0[5], a, io, m p0[3], a, io, m p0[1], a, i, m p2[7], m p2[5], m 43 44 45 46 47 48 49 50 51 52 53 54 55 56 p2[2], a, i, m p2[0], a, i, m p4[6], m p4[4], m p4[2], m p4[0], m p3[6], m p3[4], m p3[2], m p3[0], m p5[6], m p5[4], m p5[2], m p5[0], m 42 41 40 39 38 37 36 35 34 33 32 31 30 29 extclk, [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 9 of 51 8.2 56-pin part pinout (with xres) table 8-2. 56-pin part pinout (qfn [4] ) pin no. type name description figure 8-2. cy8c24894 56-pin psoc device digital analog 1 i/o i, m p2[3] direct switched capacitor block input 2 i/o i, m p2[1] direct switched capacitor block input 3 i/o m p4[7] 4 i/o m p4[5] 5 i/o m p4[3] 6 i/o m p4[1] 7 i/o m p3[7] 8 i/o m p3[5] 9 i/o m p3[3] 10 i/o m p3[1] 11 i/o m p5[7] 12 i/o m p5[5] 13 i/o m p5[3] 14 i/o m p5[1] 15 i/o m p1[7] i 2 c scl 16 i/o m p1[5] i 2 c sda 17 i/o m p1[3] 18 i/o m p1[1] i 2 c scl, issp sclk [3] 19 power v ss ground connection 20 usb d+ 21 usb d- 22 power v dd supply voltage 23 i/o p7[7] 24 i/o p7[0] 25 i/o m p1[0] i 2 c sda, issp sdata [3] 26 i/o m p1[2] 27 i/o m p1[4] optional extclk 28 i/o m p1[6] 29 i/o m p5[0] pin no. type name description 30 i/o m p5[2] digital analog 31 i/o m p5[4] 44 i/o m p2[6] external vref input 32 i/o m p5[6] 45 i/o i, m p0[0] analog column mux input 33 i/o m p3[0] 46 i/o i, m p0[2] analog column mux input 34 i/o m p3[2] 47 i/o i, m p0[4] analog column mux input vref 35 i/o m p3[4] 48 i/o i, m p0[6] analog column mux input 36 input xres active high external reset with internal pull-down 49 power v dd supply voltage 37 i/o m p4[0] 50 power v ss ground connection 38 i/o m p4[2] 51 i/o i, m p0[7] analog column mux input 39 i/o m p4[4] 52 i/o i/o, m p0[5] analog column mux input and column output 40 i/o m p4[6] 53 i/o i/o, m p0[3] analog column mux input and column output 41 i/o i, m p2[0] direct switched capacitor block input 54 i/o i, m p0[1] analog column mux input 42 i/o i, m p2[2] direct switched capacitor block input 55 i/o m p2[7] 43 i/o m p2[4] external agnd input 56 i/o mp2[5] legend a = analog, i = input, o = output, and m = analog mux input. qfn (top view) a, i, m, p2[3] a, i, m, p2[1] m, p 4 [7 ] m, p 4 [5 ] m, p 4 [3 ] m, p 4 [1 ] m, p 3 [7 ] m, p 3 [5 ] m, p 3 [3 ] m, p 3 [1 ] m, p 5 [7 ] m, p 5 [5 ] m, p 5 [3 ] m, p 5 [1 ] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 m, i2c scl, p1[7] m, i2c sda, p1[5] m, p1[3] m, i2c scl, p1[1] vss d+ d- vdd p7[7] p7[0] m, i2c sda, p1[0] m, p1[2] m, p1[4] m, p1[6] 15 16 17 18 19 20 21 22 23 24 25 26 27 28 p2[4], m p2[6], m p0[0], a, i, m p0[2], a, i, m p0[4], a, i, m p0[6], a, i, m vdd vss p0[7], a, i, m p0[5], a, io, m p0[3], a, io, m p0[1], a, i, m p2[7], m p2[5], m 43 44 45 46 47 48 49 50 51 52 53 54 55 56 p2[2], a, i, m p2[0], a, i, m p4[6], m p4[4], m p4[2], m p4[0], m xr es p3[4], m p3[2], m p3[0], m p5[6], m p5[4], m p5[2], m p5[0], m 42 41 40 39 38 37 36 35 34 33 32 31 30 29 extclk, notes 3. these are the issp pins, which are not high z at por. see the psoc technical reference manual for details. 4. the center pad on the qfn package should be connected to ground (v ss ) for best mechanical, thermal, and electrical performance. if not connected to ground, it should be electrically floated and not connected to any other signal. [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 10 of 51 8.3 68-pin part pinout the following 68-pin qfn part table and drawing is for the cy8c24994 psoc device. table 8-3. 68-pin part pinout (qfn [5] ) pin no. type name description figure 8-3. cy8c24994 68-pin psoc device digital analog 1 i/o m p4[7] 2 i/o m p4[5] 3 i/o mp4[3] 4 i/o mp4[1] 5 nc no connection 6 nc no connection 7 power v ss ground connection 8 i/o m p3[7] 9 i/o m p3[5] 10 i/o mp3[3] 11 i/o mp3[1] 12 i/o m p5[7] 13 i/o m p5[5] 14 i/o mp5[3] 15 i/o mp5[1] 16 i/o m p1[7] i 2 c scl 17 i/o m p1[5] i 2 c sda 18 i/o m p1[3] 19 i/o m p1[1] i2c scl issp sclk [6] 20 power v ss ground connection 21 usb d+ 22 usb d- 23 power v dd supply voltage 24 i/o p7[7] 25 i/o p7[6] 26 i/o p7[5] 27 i/o p7[4] 28 i/o p7[3] 29 i/o p7[2] pin no. type name description 30 i/o p7[1] digital analog 31 i/o p7[0] 50 i/o m p4[6] 32 i/o m p1[0] i 2 c sda, issp sdata [6] 51 i/o i,m p2[0] direct switched capacitor block input 33 i/o m p1[2] 52 i/o i,m p2[2] direct switched capacitor block input 34 i/o m p1[4] optional extclk 53 i/o m p2[4] external agnd input 35 i/o m p1[6] 54 i/o m p2[6] external vref input 36 i/o m p5[0] 55 i/o i,m p0[0] analog column mux input 37 i/o m p5[2] 56 i/o i,m p0[2] analog column mux input and column output 38 i/o m p5[4] 57 i/o i,m p0[4] analog column mux input and column output 39 i/o m p5[6] 58 i/o i,m p0[6] analog column mux input 40 i/o m p3[0] 59 power v dd supply voltage 41 i/o m p3[2] 60 power v ss ground connection 42 i/o m p3[4] 61 i/o i,m p0[7] analog column mux input, integration input #1 43 i/o m p3[6] 62 i/o i/o,m p0[5] analog column mux input and column output, integration input #2 44 nc no connection. 63 i/o i/o,m p0[3] analog column mux input and column output 45 nc no connection. 64 i/o i,m p0[1] analog column mux input 46 input xres active high pin reset with internal pull-down. 65 i/o m p2[7] 47 i/o m p4[0] 66 i/o m p2[5] 48 i/o m p4[2] 67 i/o i,m p2[3] direct switched capacitor block input 49 i/o m p4[4] 68 i/o i,m p2[1] direct switched capacitor block input legend a = analog, i = input, o = output, nc = no connection, m = analog mux input. notes 5. the center pad on the qfn package should be connected to ground (v ss ) for best mechanical, thermal, and electrical performance. if not connected to ground, it should be electrically floated and not connected to any other signal. 6. these are the issp pins, which are not high z at por. see the psoc technical reference manual for details. p2[6], m, ext. vref p2[4], m, ext. agnd m, p4[7] m, p4[5] m, p4[3] m, p4[1] nc nc vss m, p3[7] m, p3[5] m, p3[3] m, p3[1] m, p5[7] m, p5[5] m, p5[3] m, p5[1] i2c scl, m, p1[7] i2c sda, m, p1[5] m, p1[3] p7[5] i2c sda, m, p1[0] i2c scl, m, p1[1] vss d + d - vdd p7[6] p7[4] p7[3] p7[2] p7[1] p7[0] m, p1[2] p2[0], m, ai p4[6], m p4[4], m p4[2], m p4[0], m xres nc nc p3[6], m p3[4], m p3[2], m p3[0], m p5[6], m p5[4], m p5[2], m p5[0], m p1[6], m p2[1], m, ai p2[3], m, ai p2[5], m p2[7], m p0[1], m, ai p0[3], m, aio p0[5], m, aio p0[7], m, ai vss vdd p0[6], m, ai p0[4], m, ai p0[2], m, ai p0[0], m, ai p2[2], m, ai 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 qfn (top view) m, p1[4] extclk, p7[7] [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 11 of 51 8.4 68-pin part pinout (on-chip debug) the following 68-pin qfn part table and drawing is for the cy8c24094 ocd psoc device. note this part is only used for in-circuit d ebugging. it is not available for production. table 8-4. 68-pin part pinout (qfn [7] ) pin no. type name description figure 8-4. cy8c240 94 68-pin ocd psoc device digital analog 1 i/o m p4[7] 2 i/o m p4[5] 3 i/o mp4[3] 4 i/o mp4[1] 5 ocde ocd even data i/o 6 ocdo ocd odd data output 7 power v ss ground connection 8 i/o m p3[7] 9 i/o m p3[5] 10 i/o mp3[3] 11 i/o mp3[1] 12 i/o m p5[7] 13 i/o m p5[5] 14 i/o mp5[3] 15 i/o mp5[1] 16 i/o m p1[7] i 2 c scl 17 i/o m p1[5] i 2 c sda 18 i/o m p1[3] 19 i/o mp1[1]i 2 c scl, issp sclk [8] 20 power v ss ground connection 21 usb d+ 22 usb d- 23 power v dd supply voltage 24 i/o p7[7] 25 i/o p7[6] 26 i/o p7[5] 27 i/o p7[4] 28 i/o p7[3] 29 i/o p7[2] pin no. type name description 30 i/o p7[1] digital analog 31 i/o p7[0] 50 i/o m p4[6] 32 i/o m p1[0] i 2 c sda, issp sdata [8] 51 i/o i,m p2[0] direct switched capacitor block input 33 i/o m p1[2] 52 i/o i,m p2[2] direct switched capacitor block input 34 i/o m p1[4] optional extclk 53 i/o m p2[4] external agnd input 35 i/o m p1[6] 54 i/o m p2[6] external vref input 36 i/o m p5[0] 55 i/o i,m p0[0] analog column mux input 37 i/o m p5[2] 56 i/o i,m p0[2] analog column mux input and column output 38 i/o m p5[4] 57 i/o i,m p0[4] analog column mux input and column output 39 i/o m p5[6] 58 i/o i,m p0[6] analog column mux input 40 i/o m p3[0] 59 power v dd supply voltage 41 i/o m p3[2] 60 power v ss ground connection 42 i/o m p3[4] 61 i/o i,m p0[7] analog column mux input, integration input #1 43 i/o m p3[6] 62 i/o i/o,m p0[5] analog column mux input and column output, integration input #2 44 hclk ocd high speed clock output 63 i/o i/o,m p0[3] analog column mux input and column output 45 cclk ocd cpu clock output 64 i/o i,m p0[1] analog column mux input 46 input xres active high pin reset with internal pull-down 65 i/o m p2[7] 47 i/o m p4[0] 66 i/o m p2[5] 48 i/o m p4[2] 67 i/o i,m p2[3] direct switched capacitor block input 49 i/o m p4[4] 68 i/o i,m p2[1] direct switched capacitor block input legend a = analog, i = input, o = output, m = analog mux input, ocd = on-chip debugger. notes 7. the center pad on the qfn package should be connected to ground (v ss ) for best mechanical, thermal, and electrical performance. if not connected to ground, it should be electrically floated and not connected to any other signal. 8. these are the issp pins, which are not high z at por. see the psoc technical reference manual for details. m, p4[7] m, p4[5] m, p4[3] m, p4[1] ocde ocdo vss m, p3[7] m, p3[5] m, p3[3] m, p3[1] m, p5[7] m, p5[5] m, p5[3] m, p5[1] i2c scl, m, p1[7] i2c sda, m, p1[5] m, p1[3] p7[5] i2c sda, m, p1[0] i2c scl, m, p1[1] vss d + d - vdd p7[7] p7[6] p7[4] p7[3] p7[2] p7[1] p7[0] m, p1[2] m, p1[4] p2[0], m, ai p4[6], m p4[4], m p4[2], m p4[0], m xres cclk hclk p3[6], m p3[4], m p3[2], m p3[0], m p5[6], m p5[4], m p5[2], m p5[0], m p1[6], m p2[1], m, ai p2[3], m, ai p2[5], m p2[7], m p0[1], m, ai p0[3], m, aio p0[5], m, aio p0[7], m, ai vss vdd p0[6], m, ai p0[4], m, ai p0[2], m, ai p0[0], m, ai p2[6], m, ext. vref p2[4], m, ext. agnd p2[2], m, ai 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 qfn (top view) extclk , [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 12 of 51 8.5 100-ball vfbga part pinout the 100-ball vfbga part is for the cy8c24994 psoc device. table 8-5. 100-ball part pinout (vfbga) pin no. digital analog name description pin no. digital analog name description a1 power v ss ground connection f1 nc no connection a2 power v ss ground connection f2 i/o m p5[7] a3 nc no connection f3 i/o m p3[5] a4 nc no connection f4 i/o m p5[1] a5 nc no connection f5 power v ss ground connection a6 power v dd supply voltage f6 power v ss ground connection a7 nc no connection f7 i/o m p5[0] a8 nc no connection f8 i/o m p3[0] a9 power v ss ground connection f9 xres active high pin reset with internal pull-down a10 power v ss ground connection f10 i/o p7[1] b1 power v ss ground connection g1 nc no connection b2 power v ss ground connection g2 i/o m p5[5] b3 i/o i,m p2[1] direct switched capacitor block input g3 i/o m p3[3] b4 i/o i,m p0[1] analog column mux input g4 i/o m p1[7] i 2 c scl b5 i/o i,m p0[7] analog column mux input g5 i/o m p1[1] i 2 c scl, issp sclk [9] b6 power v dd supply voltage g6 i/o m p1[0] i 2 c sda, issp sdata [9] b7 i/o i,m p0[2] analog column mux input g7 i/o m p1[6] b8 i/o i,m p2[2] direct switched capacitor block input g8 i/o m p3[4] b9 power v ss ground connection g9 i/o m p5[6] b10 power v ss ground connection g10 i/o p7[2] c1 nc no connection h1 nc no connection c2 i/o mp4[1] h2 i/o m p5[3] c3 i/o mp4[7] h3 i/o m p3[1] c4 i/o m p2[7] h4 i/o m p1[5] i 2 c sda c5 i/o i/o,m p0[5] analog column mux input and column output h5 i/o m p1[3] c6 i/o i,m p0[6] analog column mux input h6 i/o m p1[2] c7 i/o i,m p0[0] analog column mux input h7 i/o m p1[4] optional extclk c8 i/o i,m p2[0] direct switched capacitor block input h8 i/o m p3[2] c9 i/o mp4[2] h9 i/o m p5[4] c10 nc no connection h10 i/o p7[3] d1 nc no connection j1 power v ss ground connection d2 i/o mp3[7] j2 power v ss ground connection d3 i/o mp4[5] j3 usb d+ d4 i/o m p2[5] j4 usb d- d5 i/o i/o,m p0[3] analog column mux input and column output j5 power v dd supply voltage d6 i/o i,m p0[4] analog column mux input j6 i/o p7[7] d7 i/o m p2[6] external vref input j7 i/o p7[0] d8 i/o m p4[6] j8 i/o m p5[2] d9 i/o m p4[0] j9 power v ss ground connection d10 nc no connection j10 power v ss ground connection e1 nc no connection k1 power v ss ground connection e2 nc no connection k2 power v ss ground connection e3 i/o mp4[3] k3 nc no connection e4 i/o i,m p2[3] direct switched capacitor block input k4 nc no connection e5 power v ss ground connection k5 power v dd supply voltage e6 power v ss ground connection k6 i/o p7[6] e7 i/o m p2[4] external agnd input k7 i/o p7[5] e8 i/o m p4[4] k8 i/o p7[4] e9 i/o m p3[6] k9 power v ss ground connection e10 nc no connection k10 power v ss ground connection legend a = analog, i = input, o = output, m = analog mux input, nc = no connection. note 9. these are the issp pins, which are not high z at por. see the psoc technical reference manual for details. [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 13 of 51 figure 8-5. cy8c24094 ocd (not for production) vss vss nc nc nc vdd nc nc vss vss vss vss p2[1] p0[1] p0[7] vdd p0[2] p2[2] vss vss nc p4[1] p4[7] p2[7] p0[5] p0[6] p0[0] p2[0] p4[2] nc nc p3[7] p4[5] p2[5] p0[3] p0[4] p2[6] p4[6] p4[0] nc nc nc p4[3] p2[3] vss vss p2[4] p4[4] p3[6] nc nc p5[7] p3[5] p5[1] vss vss p5[0] p3[0] xres p7[1] nc p5[5] p3[3] p1[7] p1[1] p1[0] p1[6] p3[4] p5[6] p7[2] nc p5[3] p3[1] p1[5] p1[3] p1[2] p1[4] p3[2] p5[4] p7[3] vss vss d + d - vdd p7[7] p7[0] p5[2] vss vss vss vss nc nc vdd p7[6] p7[5] p7[4] vss vss 12345678910 a b c d e f g h j k bga (top view) [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 14 of 51 8.6 100-ball vfbga part pinout (on-chip debug) the following 100-pin vfbga part table and drawing is for the cy8c24094 ocd psoc device. note this part is only used for in-circuit d ebugging. it is not available for production. table 8-6. 100-ball part pinout (vfbga) pin no. digital analog name description pin no. digital analog name description a1 power v ss ground connection f1 ocde ocd even data i/o a2 power v ss ground connection f2 i/o m p5[7] a3 nc no connection f3 i/o m p3[5] a4 nc no connection f4 i/o m p5[1] a5 nc no connection. f5 power v ss ground connection a6 power v dd supply voltage. f6 power v ss ground connection a7 nc no connection. f7 i/o m p5[0] a8 nc no connection. f8 i/o m p3[0] a9 power v ss ground connection f9 xres active high pin reset with internal pull-down a10 power v ss ground connection f10 i/o p7[1] b1 power v ss ground connection g1 ocdo ocd odd data output b2 power v ss ground connection g2 i/o m p5[5] b3 i/o i,m p2[1] direct switched capacitor block input g3 i/o m p3[3] b4 i/o i,m p0[1] analog column mux input g4 i/o m p1[7] i 2 c scl b5 i/o i,m p0[7] analog column mux input g5 i/o m p1[1] i 2 c scl , issp sclk [10] b6 power v dd supply voltage g6 i/o m p1[0] i 2 c sda , issp sdata [10] b7 i/o i,m p0[2] analog column mux input g7 i/o m p1[6] b8 i/o i,m p2[2] direct switched capacitor block input g8 i/o m p3[4] b9 power v ss ground connection g9 i/o m p5[6] b10 power v ss ground connection g10 i/o p7[2] c1 nc no connection h1 nc no connection c2 i/o mp4[1] h2 i/o m p5[3] c3 i/o mp4[7] h3 i/o m p3[1] c4 i/o m p2[7] h4 i/o m p1[5] i 2 c sda c5 i/o i/o, m p0[5] analog column mux input and column output h5 i/o m p1[3] c6 i/o i,m p0[6] analog column mux input h6 i/o m p1[2] c7 i/o i,m p0[0] analog column mux input h7 i/o m p1[4] optional extclk c8 i/o i,m p2[0] direct switched capacitor block input h8 i/o m p3[2] c9 i/o mp4[2] h9 i/o m p5[4] c10 nc no connection h10 i/o p7[3] d1 nc no connection j1 power v ss ground connection d2 i/o mp3[7] j2 power v ss ground connection d3 i/o mp4[5] j3 usb d+ d4 i/o m p2[5] j4 usb d- d5 i/o i/o, m p0[3] analog column mux input and column output j5 power v dd supply voltage d6 i/o i,m p0[4] analog column mux input j6 i/o p7[7] d7 i/o m p2[6] external vref input j7 i/o p7[0] d8 i/o m p4[6] j8 i/o m p5[2] d9 i/o m p4[0] j9 power v ss ground connection d10 cclk ocd cpu clock output j10 power v ss ground connection e1 nc no connection k1 power v ss ground connection e2 nc no connection k2 power v ss ground connection e3 i/o mp4[3] k3 nc no connection e4 i/o i,m p2[3] direct switched capacitor block input k4 nc no connection e5 power v ss ground connection k5 power v dd supply voltage e6 power v ss ground connection k6 i/o p7[6] e7 i/o m p2[4] external agnd input k7 i/o p7[5] e8 i/o m p4[4] k8 i/o p7[4] e9 i/o m p3[6] k9 power v ss ground connection e10 hclk ocd high speed clock output k10 power v ss ground connection legend a = analog, i = input, o = output, m = analog mux input, nc = no connection , ocd = on-chip debugger. note 10. these are the issp pins, which are not high z at por. see the psoc technical reference manual for details. [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 15 of 51 figure 8-6. cy8c24094 ocd (not for production) vss vss nc nc nc vdd nc nc vss vss vss vss p2[1] p0[1] p0[7] vdd p0[2] p2[2] vss vss nc p4[1] p4[7] p2[7] p0[5] p0[6] p0[0] p2[0] p4[2] nc nc p3[7] p4[5] p2[5] p0[3] p0[4] p2[6] p4[6] p4[0] cclk nc nc p4[3] p2[3] vss vss p2[4] p4[4] p3[6] hclk ocde p5[7] p3[5] p5[1] vss vss p5[0] p3[0] xres p7[1] ocdo p5[5] p3[3] p1[7] p1[1] p1[0] p1[6] p3[4] p5[6] p7[2] nc p5[3] p3[1] p1[5] p1[3] p1[2] p1[4] p3[2] p5[4] p7[3] vss vss d + d - vdd p7[7] p7[0] p5[2] vss vss vss vss nc nc vdd p7[6] p7[5] p7[4] vss vss 12345678910 a b c d e f g h j k bga (top view) [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 16 of 51 8.7 100-pin part pinout (on-chip debug) the 100-pin tqfp part is for the cy8c24094 ocd psoc device. note this part is only used for in-circuit d ebugging. it is not available for production. table 8-7. 100-pin part pinout (tqfp) pin no. digital analog name description pin no. digital analog name description 1 nc no connection 51 i/o m p1[6] 2 nc no connection 52 i/o m p5[0] 3 i/o i, m p0[1] analog column mux input 53 i/o m p5[2] 4 i/o m p2[7] 54 i/o m p5[4] 5 i/o m p2[5] 55 i/o m p5[6] 6 i/o i, m p2[3] direct switched capacitor block input 56 i/o m p3[0] 7 i/o i, m p2[1] direct switched capacitor block input 57 i/o m p3[2] 8 i/o m p4[7] 58 i/o m p3[4] 9 i/o m p4[5] 59 i/o m p3[6] 10 i/o m p4[3] 60 hclk ocd high speed clock output 11 i/o m p4[1] 61 cclk ocd cpu clock output 12 ocde ocd even data i/o 62 input xres active high pin reset with internal pull-down 13 ocdo ocd odd data output 63 i/o m p4[0] 14 nc no connection 64 i/o m p4[2] 15 power v ss ground connection 65 power v ss ground connection 16 i/o m p3[7] 66 i/o m p4[4] 17 i/o m p3[5] 67 i/o m p4[6] 18 i/o m p3[3] 68 i/o i, m p2[0] direct switched capacitor block input 19 i/o m p3[1] 69 i/o i, m p2[2] direct switched capacitor block input 20 i/o m p5[7] 70 i/o p2[4] external agnd input 21 i/o m p5[5] 71 nc no connection 22 i/o m p5[3] 72 i/o p2[6] external vref input 23 i/o m p5[1] 73 nc no connection 24 i/o m p1[7] i 2 c scl 74 i/o i p0[0] analog column mux input 25 nc no connection 75 nc no connection 26 nc no connection 76 nc no connection 27 nc no connection 77 i/o i, m p0[2] analog column mux input and column output 28 i/o p1[5] i 2 c sda 78 nc no connection 29 i/o p1[3] 79 i/o i, m p0[4] analog column mux input and column output 30 i/o p1[1] crystal (xtalin), i2c scl, issp sclk [11] 80 nc no connection 31 nc no connection 81 i/o i, m p0[6] analog column mux input 32 power v ss ground connection 82 power v dd supply voltage 33 usb d+ 83 nc no connection 34 usb d- 84 power v ss ground connection 35 power v dd supply voltage 85 nc no connection 36 i/o p7[7] 86 nc no connection 37 i/o p7[6] 87 nc no connection 38 i/o p7[5] 88 nc no connection 39 i/o p7[4] 89 nc no connection 40 i/o p7[3] 90 nc no connection 41 i/o p7[2] 91 nc no connection 42 i/o p7[1] 92 nc no connection 43 i/o p7[0] 93 nc no connection 44 nc no connection 94 nc no connection 45 nc no connection 95 i/o i, m p0[7] analog column mux input 46 nc no connection 96 nc no connection 47 nc no connection 97 i/o i/o, m p0[5] analog column mux input and column output 48 i/o p1[0] crystal (xtalout), i2c sda, issp sdata [11] 98 nc no connection 49 i/o p1[2] 99 i/o i/o, m p0[3] analog column mux input and column output 50 i/o p1[4] optional extclk 100 nc no connection legend a = analog, i = input, o = output, nc = no connection, m = analog mux input, ocd = on-chip debugger. note 11. these are the issp pins, which are not high z at por. see the psoc technical reference manual for details. [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 17 of 51 figure 8-7. cy8c24094 ocd (not for production) tqfp nc nc ai, m, p0[1] m, p2[7] m, p2[5] ai, m, p2[3] ai, m, p2[1] m, p4[7] m, p4[5] m, p4[3] m, p4[1] ocde ocdo nc vss m, p3[7] m, p3[5] m, p3[3] m, p3[1] m, p5[7] m, p5[5] m, p5[3] m, p5[1] i2c scl, p1[7] nc nc d- p7[3] nc nc i2c sda, m, p1[5] m, p1[3] i2c scl, m, p1[1] nc vss d+ vdd p7[7] p7[6] p7[5] p7[4] p7[2] p7[1] p7[0] nc nc nc i2c sda, m, p1[0] m, p1[2] m, p1[4] nc p0[0], m, ai nc p2[6], m, external vref nc p2[4], m, external agnd p2[2], m, ai p2[0], m, ai p4[6], m p4[4], m vss p4[2], m p4[0], m xres cclk hclk p3[6], m p3[4], m p3[2], m p3[0], m p5[6], m p5[4], m p5[2], m p5[0], m p1[6], m nc p0[3], m, ai nc p0[5], m, ai nc p0[7], m, ai nc nc nc nc nc nc nc nc nc nc vss nc vdd p0[6], m, ai nc p0[4], m, ai nc p0[2], m, ai nc 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 50 49 extclk, [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 18 of 51 9. register reference this section lists the registers of the cy8c24x94 psoc de vice family. for detailed register information, see the psoc technical reference manual . 9.1 register conventions the register conventions specific to this section are listed in the following table. 9.2 register mapping tables the psoc device has a total register address space of 512 bytes. the register space is referred to as i/o space and is divided into two banks. the xoi bit in the flag register (cpu_f) determines which bank the user is currently in. when the xoi bit is set the user is in bank 1. note in the following register mapping tables, blank fields are reserved and should not be accessed. convention description r read register or bit(s) w write register or bit(s) l logical register or bit(s) c clearable register or bit(s) # access is bit specific [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 19 of 51 9.3 register map bank 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw pma0_dr 40 rw asc10cr0 80 rw c0 prt0ie 01 rw pma1_dr 41 rw asc10cr1 81 rw c1 prt0gs 02 rw pma2_dr 42 rw asc10cr2 82 rw c2 prt0dm2 03 rw pma3_dr 43 rw asc10cr3 83 rw c3 prt1dr 04 rw pma4_dr 44 rw asd11cr0 84 rw c4 prt1ie 05 rw pma5_dr 45 rw asd11cr1 85 rw c5 prt1gs 06 rw pma6_dr 46 rw asd11cr2 86 rw c6 prt1dm2 07 rw pma7_dr 47 rw asd11cr3 87 rw c7 prt2dr 08 rw usb_sof0 48 r 88 c8 prt2ie 09 rw usb_sof1 49 r 89 c9 prt2gs 0a rw usb_cr0 4a rw 8a ca prt2dm2 0b rw usbi/o_cr0 4b # 8b cb prt3dr 0c rw usbi/o_cr1 4c rw 8c cc prt3ie 0d rw 4d 8d cd prt3gs 0e rw ep1_cnt1 4e # 8e ce prt3dm2 0f rw ep1_cnt 4f rw 8f cf prt4dr 10 rw ep2_cnt1 50 # asd20cr0 90 rw cur_pp d0 rw prt4ie 11 rw ep2_cnt 51 rw asd20cr1 91 rw stk_pp d1 rw prt4gs 12 rw ep3_cnt1 52 # asd20cr2 92 rw d2 prt4dm2 13 rw ep3_cnt 53 rw asd20cr3 93 rw idx_pp d3 rw prt5dr 14 rw ep4_cnt1 54 # asc21cr0 94 rw mvr_pp d4 rw prt5ie 15 rw ep4_cnt 55 rw asc21cr1 95 rw mvw_pp d5 rw prt5gs 16 rw ep0_cr 56 # asc21cr2 96 rw i2c_cfg d6 rw prt5dm2 17 rw ep0_cnt 57 # asc21cr3 97 rw i2c_scr d7 # 18 ep0_dr0 58 rw 98 i2c_dr d8 rw 19 ep0_dr1 59 rw 99 i2c_mscr d9 # 1a ep0_dr2 5a rw 9a int_clr0 da rw 1b ep0_dr3 5b rw 9b int_clr1 db rw prt7dr 1c rw ep0_dr4 5c rw 9c int_clr2 dc rw prt7ie 1d rw ep0_dr5 5d rw 9d int_clr3 dd rw prt7gs 1e rw ep0_dr6 5e rw 9e int_msk3 de rw prt7dm2 1f rw ep0_dr7 5f rw 9f int_msk2 df rw dbb00dr0 20 # amx_in 60 rw a0 int_msk0 e0 rw dbb00dr1 21 w amuxcfg 61 rw a1 int_msk1 e1 rw dbb00dr2 22 rw 62 a2 int_vc e2 rc dbb00cr0 23 # arf_cr 63 rw a3 res_wdt e3 w dbb01dr0 24 # cmp_cr0 64 # a4 dec_dh e4 rc dbb01dr1 25 w asy_cr 65 # a5 dec_dl e5 rc dbb01dr2 26 rw cmp_cr1 66 rw a6 dec_cr0 e6 rw dbb01cr0 27 # 67 a7 dec_cr1 e7 rw dcb02dr0 28 # 68 mul1_x a8 w mul0_x e8 w dcb02dr1 29 w 69 mul1_y a9 w mul0_y e9 w dcb02dr2 2a rw 6a mul1_dh aa r mul0_dh ea r dcb02cr0 2b # 6b mul1_dl ab r mul0_dl eb r dcb03dr0 2c # tmp_dr0 6c rw acc1_dr1 ac rw acc0_dr1 ec rw dcb03dr1 2d w tmp_dr1 6d rw acc1_dr0 ad rw acc0_dr0 ed rw dcb03dr2 2e rw tmp_dr2 6e rw acc1_dr3 ae rw acc0_dr3 ee rw dcb03cr0 2f # tmp_dr3 6f rw acc1_dr2 af rw acc0_dr2 ef rw 30 acb00cr3 70 rw rdi0ri b0 rw f0 31 acb00cr0 71 rw rdi0syn b1 rw f1 32 acb00cr1 72 rw rdi0is b2 rw f2 33 acb00cr2 73 rw rdi0lt0 b3 rw f3 34 acb01cr3 74 rw rdi0lt1 b4 rw f4 35 acb01cr0 75 rw rdi0ro0 b5 rw f5 36 acb01cr1 76 rw rdi0ro1 b6 rw f6 37 acb01cr2 77 rw b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fa 3b 7b bb fb 3c 7c bc fc 3d 7d bd dac_d fd rw 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific. [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 20 of 51 9.4 register map bank 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw pma0_wa 40 rw asc10cr0 80 rw usbi/o_cr2 c0 rw prt0dm1 01 rw pma1_wa 41 rw asc10cr1 81 rw usb_cr1 c1 # prt0ic0 02 rw pma2_wa 42 rw asc10cr2 82 rw prt0ic1 03 rw pma3_wa 43 rw asc10cr3 83 rw prt1dm0 04 rw pma4_wa 44 rw asd11cr0 84 rw ep1_cr0 c4 # prt1dm1 05 rw pma5_wa 45 rw asd11cr1 85 rw ep2_cr0 c5 # prt1ic0 06 rw pma6_wa 46 rw asd11cr2 86 rw ep3_cr0 c6 # prt1ic1 07 rw pma7_wa 47 rw asd11cr3 87 rw ep4_cr0 c7 # prt2dm0 08 rw 48 88 c8 prt2dm1 09 rw 49 89 c9 prt2ic0 0a rw 4a 8a ca prt2ic1 0b rw 4b 8b cb prt3dm0 0c rw 4c 8c cc prt3dm1 0d rw 4d 8d cd prt3ic0 0e rw 4e 8e ce prt3ic1 0f rw 4f 8f cf prt4dm0 10 rw pma0_ra 50 rw 90 gdi_o_in d0 rw prt4dm1 11 rw pma1_ra 51 rw asd20cr1 91 rw gdi_e_in d1 rw prt4ic0 12 rw pma2_ra 52 rw asd20cr2 92 rw gdi_o_ou d2 rw prt4ic1 13 rw pma3_ra 53 rw asd20cr3 93 rw gdi_e_ou d3 rw prt5dm0 14 rw pma4_ra 54 rw asc21cr0 94 rw d4 prt5dm1 15 rw pma5_ra 55 rw asc21cr1 95 rw d5 prt5ic0 16 rw pma6_ra 56 rw asc21cr2 96 rw d6 prt5ic1 17 rw pma7_ra 57 rw asc21cr3 97 rw d7 18 58 98 mux_cr0 d8 rw 19 59 99 mux_cr1 d9 rw 1a 5a 9a mux_cr2 da rw 1b 5b 9b mux_cr3 db rw prt7dm0 1c rw 5c 9c dc prt7dm1 1d rw 5d 9d osc_go_en dd rw prt7ic0 1e rw 5e 9e osc_cr4 de rw prt7ic1 1f rw 5f 9f osc_cr3 df rw dbb00fn 20 rw clk_cr0 60 rw a0 osc_cr0 e0 rw dbb00in 21 rw clk_cr1 61 rw a1 osc_cr1 e1 rw dbb00ou 22 rw abf_cr0 62 rw a2 osc_cr2 e2 rw 23 amd_cr0 63 rw a3 vlt_cr e3 rw dbb01fn 24 rw cmp_go_en 64 rw a4 vlt_cmp e4 r dbb01in 25 rw 65 a5 e5 dbb01ou 26 rw amd_cr1 66 rw a6 e6 27 alt_cr0 67 rw a7 e7 dcb02fn 28 rw 68 a8 imo_tr e8 w dcb02in 29 rw 69 a9 ilo_tr e9 w dcb02ou 2a rw 6a aa bdg_tr ea rw 2b 6b ab eco_tr eb w dcb03fn 2c rw tmp_dr0 6c rw ac mux_cr4 ec rw dcb03in 2d rw tmp_dr1 6d rw ad mux_cr5 ed rw dcb03ou 2e rw tmp_dr2 6e rw ae ee 2f tmp_dr3 6f rw af ef 30 acb00cr3 70 rw rdi0ri b0 rw f0 31 acb00cr0 71 rw rdi0syn b1 rw f1 32 acb00cr1 72 rw rdi0is b2 rw f2 33 acb00cr2 73 rw rdi0lt0 b3 rw f3 34 acb01cr3 74 rw rdi0lt1 b4 rw f4 35 acb01cr0 75 rw rdi0ro0 b5 rw f5 36 acb01cr1 76 rw rdi0ro1 b6 rw f6 37 acb01cr2 77 rw b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fa 3b 7b bb fb 3c 7c bc fc 3d 7d bd dac_cr fd rw 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific. [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 21 of 51 10. electrical specifications this section presents the dc and ac electric al specifications of the cy8c24x94 psoc device family. for the most up to date elec trical specifications, confirm that you have th e most recent data sheet by visiting http://www.cypress.com . specifications are valid for ?40 c t a 85 c and t j 100 c, except where noted. specificatio ns for devices running at greater than 12 mhz are valid for ?40 c t a 70 c and t j 82 c. figure 10-1. voltage versus cpu frequency 5.25 4.75 3.00 93 khz 12 mhz 24 mhz cpu frequency vdd voltage v a l i d o p e r a t i n g r e g i o n [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 22 of 51 10.1 absolute maximum ratings 10.2 operating temperature table 10-1. absolu te maximum ratings symbol description min typ max units notes t stg storage temperature ?55 25 +100 c higher storage temperatures reduces data retention time. recommended storage temperature is +25 c 25 c. extended duration storage temperatures above 65 c degrades reliability. t baketemp bake temperature ? 125 see package label c t baketime bake time see package label ? 72 hours t a ambient temperature with power applied ?40 ? +85 c v dd supply voltage on v dd relative to v ss ?0.5 ? +6.0 v v i/o dc input voltage v ss ? 0.5 ? v dd + 0.5 v v i/o2 dc voltage applied to tristate v ss ? 0.5 ? v dd + 0.5 v i mi/o maximum current into any port pin ?25 ? +50 ma i mai/o maximum current into any port pin configured as analog driver ?50 ? +50 ma esd electrostatic discharge voltage 2000 ? ? v human body model esd. lu latch-up current ? ? 200 ma table 10-2. operating temperature symbol description min typ max units notes t a ambient temperature ?40 ? +85 c t ausb ambient temperature using usb ?10 ? +85 c t j junction temperature ?40 ? +100 c the temperature rise from ambient to junction is package specific. see thermal impedance on page 43. the user must limit the power consumption to comply with this requirement. [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 23 of 51 10.3 dc electrical characteristics 10.3.1 dc chip-level specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. 10.3.2 dc general-purpose i/o specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 10-3. dc chip-level specifications symbol description min typ max units notes v dd supply voltage 3.0 ? 5.25 v see dc por and lvd specifications, table 10-13 on page 29. i dd5 supply current, imo = 24 mhz (5 v) ? 14 27 ma conditions are v dd = 5.0 v, t a = 25 c, cpu = 3 mhz, sysclk doubler disabled, vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 93.75 khz, analog power = off. i dd3 supply current, imo = 24 mhz (3.3 v) ? 8 14 ma conditions are v dd = 3.3 v, t a = 25 c, cpu = 3 mhz, sysclk doubler disabled, vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 0.367 khz, analog power = off. i sb sleep (mode) current with por, lvd, sleep timer, and wdt. [12] ? 3 6.5 a conditions are with internal slow speed oscillator, v dd = 3.3 v, ?40 c t a 55 c, analog power = off. i sbh sleep (mode) current with por, lvd, sleep timer, and wdt at high temperature. [12] ? 4 25 a conditions are with internal slow speed oscillator, v dd = 3.3 v, 55 c < t a 85 c, analog power = off. table 10-4. dc gpio specifications symbol description min typ max units notes r pu pull-up resistor 4 5.6 8 k r pd pull-down resistor 4 5.6 8 k v oh high output level v dd ? 1.0 ? ? v i oh = 10 ma, v dd = 4.75 to 5.25 v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0 [3], p1[5])). 80 ma maximum combined i oh budget. v ol low output level ? ? 0.75 v i ol = 25 ma, v dd = 4.75 to 5.25 v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])). 200 ma maximum combined i ol budget. i oh high level source current 10 ? ? ma v oh = v dd -1.0 v, see the limitations of the total current in the note for v oh i ol low level sink current 25 ? ? ma v ol = 0.75 v, see the limitations of the total current in the note for v ol v il input low level ? ? 0.8 v v dd = 3.0 to 5.25. v ih input high level 2.1 ? v v dd = 3.0 to 5.25. v h input hysterisis ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a. c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. temp = 25 c. c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. temp = 25 c. note 12. standby current includes all functions (por, lvd, wdt, sleep time) needed for reliable system operation. this should be comp ared with devices that have similar functions enabled. [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 24 of 51 10.3.3 dc full-speed usb specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?10 c t a 85 c, or 3.0 v to 3.6 v and ?10 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. 10.3.4 dc operational amplifier specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temper ature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. the operational amplifier is a component of both the analog co ntinuous time psoc blocks and the analog switched capacitor psoc blocks. the guaranteed sp ecifications are measured in the analog continuous ti me psoc block. table 10-5. dc full-speed (12 mbps) usb specifications symbol description min typ max units notes usb interface v di differential input sensitivity 0.2 ? ? v | (d+) - (d-) | v cm differential input common mode range 0.8 ? 2.5 v v se single ended receiver threshold 0.8 ? 2.0 v c in transceiver capacitance ? ? 20 pf i i/o high z state data line leakage ?10 ? 10 a0 v < v in < 3.3 v. r ext external usb series resistor 23 ? 25 w in series with each usb pin. v uoh static output high, driven 2.8 ? 3.6 v 15 k 5% to ground. internal pull-up enabled. v uohi static output high, idle 2.7 ? 3.6 v 15 k 5% to ground. internal pull-up enabled. v uol static output low ? ? 0.3 v 15 k 5% to ground. internal pull-up enabled. z o usb driver output impedance 28 ? 44 w including r ext resistor. v crs d+/d- crossover voltage 1.3 ? 2.0 v table 10-6. 5-v dc operational amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high ? ? ? 1.6 1.3 1.2 10 8 7.5 mv mv mv tcv osoa average input offset voltage drift ? 7.0 35.0 v/ c i eboa input leakage current (port 0 analog pins) ? 20 ? pa gross tested to 1 a. c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. temp = 25 c. v cmoa common mode voltage range common mode voltage range (high power or high opamp bias) 0.0 ? v dd v dd ? 0.5 v the common-mode input voltage range is measured through an analog output buffer. the specification includes the limitations imposed by the characteristics of the analog output buffer. 0.5 ? g oloa open loop gain power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high 60 60 80 ??db [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 25 of 51 10.3.5 dc low-power comparator specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v at 25 c and are for design guidance only. v ohigho a high output voltage swing (internal signals) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high v dd ? 0.2 v dd ? 0.2 v dd ? 0.5 ? ? ? ? ? ? v v v v olowoa low output voltage swing (internal signals) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 0.2 0.2 0.5 v v v i soa supply current (including associated agnd buffer) power = low, opamp bias = low power = low, opamp bias = high power = medium, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? ? ? 400 500 800 1200 2400 4600 800 900 1000 1600 3200 6400 a a a a a a psrr oa supply voltage rejection ratio 65 80 ? db v ss vin (v dd ? 2.25) or (v dd ? 1.25 v) vin v dd . table 10-6. 5-v dc operational amplifier specifications (continued) symbol description min typ max units notes table 10-7. dc low-power comparator specifications symbol description min typ max units notes v reflpc low power comparator (lpc) reference voltage range 0.2 ? v dd ? 1 v i slpc lpc supply current ? 10 40 a v oslpc lpc voltage offset ? 2.5 30 mv [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 26 of 51 10.3.6 dc analog output buffer specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temper ature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 10-8. 5-v dc analog output buffer specifications symbol description min typ max units notes v osob input offset voltage (absolute value) ? 3 12 mv tcv osob average input offset voltage drift ? +6 ? v/c v cmob common mode input voltage range 0.5 ? v dd ? 1.0 v r outob output resistance power = low power = high ? ? 0.6 0.6 ? ? w w v ohighob high output voltage swing (load = 32 ohms to v dd /2) power = low power = high 0.5 v dd + 1.1 0.5 v dd + 1.1 ? ? ? ? v v v olowob low output voltage swing (load = 32 ohms to v dd/2 ) power = low power = high ? ? ? ? 0.5 v dd ? 1.3 0.5 v dd ? 1.3 v v i sob supply current including bias cell (no load) power = low power = high ? ? 1.1 2.6 5.1 8.8 ma ma psrr ob supply voltage rejection ratio 53 64 ? db (0.5 x v dd ? 1.3) v out (v dd ? 2.3). table 10-9. 3.3-v dc analog output buffer specifications symbol description min typ max units notes v osob input offset voltage (absolute value) ? 3 12 mv tcv osob average input offset voltage drift ? +6 ? v/c v cmob common mode input voltage range 0.5 - v dd ? 1.0 v r outob output resistance power = low power = high ? ? 1 1 ? ? w w v ohighob high output voltage swing (load = 1k ohms to v dd/2 ) power = low power = high 0.5 v dd + 1.0 0.5 v dd + 1.0 ? ? ? ? v v v olowob low output voltage swing (load = 1k ohms to vdd/2) power = low power = high ? ? ? ? 0.5 v dd ? 1.0 0.5 v dd ? 1.0 v v i sob supply current including bias cell (no load) power = low power = high ? 0.8 2.0 2.0 4.3 ma ma psrr ob supply voltage rejection ratio 34 64 ? db (0.5 x v dd ? 1.0) v out (0.5 v dd + 0.9). [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 27 of 51 10.3.7 dc analog reference specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temper ature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. the guaranteed specific ations are measured throu gh the analog continuous ti me psoc blocks. the power levels for agnd refer to the power of the analog continuous time psoc block. the power levels for refhi and reflo refer to the a nalog reference control register. the limits stated for agnd include the offset error of the agnd buffer local to the analog continuous time psoc block . reference control power is high. table 10-10. 5 v dc analog reference specifications symbol description min typ max units bg bandgap voltage reference 1.28 1.30 1.32 v ? agnd = v dd/2 [13, 14] v dd/2 ? 0.04 v dd/2 ? 0.01 v dd/2 + 0.007 v ? agnd = 2 x bandgap [13, 14] 2 bg ? 0.048 2 bg - 0.030 2 bg + 0.024 v ? agnd = p2[4] (p2[4] = v dd/2 ) [13, 14] p2[4] ? 0.011 p2[4] p2[4] + 0.011 v ? agnd = bandgap [13, 14] bg ? 0.009 bg + 0.008 bg + 0.016 v ? agnd = 1.6 x bandgap [13, 14] 1.6 bg ? 0.022 1.6 bg ? 0.010 1.6 bg + 0.018 v ? agnd block to block variation (agnd = v dd/2 ) [13, 14] ?0.034 0.000 0.034 v ? refhi = v dd/2 + bandgap v dd/2 + bg ? 0.10 v dd/2 + bg v dd/2 + bg + 0.10 v ? refhi = 3 x bandgap 3 x bg ? 0.06 3 x bg 3 x bg + 0.06 v ? refhi = 2 x bandgap + p2[6] (p2[6] = 1.3 v) 2 bg + p2[6] ? 0.113 2 bg + p2[6] - 0.018 2 bg + p2[6] + 0.077 v ? refhi = p2[4] + bandgap (p2[4] = v dd/2 ) p2[4] + bg ? 0.130 p2[4] + bg - 0.016 p2[4] + bg + 0.098 v ? refhi = p2[4] + p2[6] (p2[4] = v dd/2 , p2[6] = 1.3 v) p2[4] + p2[6] ? 0.133 p2[4] + p2[6] - 0.016 p2[4] + p2[6]+ 0.100 v ? refhi = 3.2 x bandgap 3.2 bg ? 0.112 3.2 x bg 3.2 bg + 0.076 v ? reflo = v dd/2 ? bandgap v dd/2 ? bg ? 0.04 v dd/2 - bg + 0.024 v dd/2 ? bg + 0.04 v ? reflo = bandgap bg ? 0.06 bg bg + 0.06 v ? reflo = 2 x bandgap - p2[6] (p2[6] = 1.3 v) 2 bg ? p2[6] ? 0.084 2 bg - p2[6] + 0.025 2 bg ? p2[6] + 0.134 v ? reflo = p2[4] ? bandgap (p2[4] = v dd/2 ) p2[4] ? bg ? 0.056 p2[4] ? bg + 0.026 p2[4] - bg + 0.107 v ? reflo = p2[4]-p2[6] (p2[4] = v dd/2 , p2[6] = 1.3 v) p2[4] ? p2[6] ? 0.057 p2[4] ? p2[6] + 0.026 p2[4] ? p2[6] + 0.110 v [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 28 of 51 10.3.8 dc analog psoc block specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 10-11. 3.3-v dc analog reference specifications symbol description min typ max units bg bandgap voltage reference 1.28 1.30 1.32 v ? agnd = v dd/2 [13, 14] v dd/2 ? 0.03 v dd/2 ? 0.01 v dd/2 + 0.005 v ? agnd = 2 x bandgap [13, 14] not allowed ? agnd = p2[4] (p2[4] = v dd/2 ) p2[4] ? 0.008 p2[4] + 0.001 p2[4] + 0.009 v ? agnd = bandgap [13, 14] bg ? 0.009 bg + 0.005 bg + 0.015 v ? agnd = 1.6 x bandgap [13, 14] 1.6 x bg ? 0.027 1.6 x bg ? 0.010 1.6 x bg + 0.018 v ? agnd column to column variation (agnd = v dd/2 ) [13, 14] ?0.034 0.000 0.034 v ? refhi = v dd/2 + bandgap not allowed ? refhi = 3 x bandgap not allowed ? refhi = 2 x bandgap + p2[6] (p2[6] = 0.5 v) not allowed ? refhi = p2[4] + bandgap (p2[4] = v dd/2 ) not allowed ? refhi = p2[4] + p2[6] (p2[4] = v dd/2 , p2[6] = 0.5 v) p2[4] + p2[6] ? 0.075 p2[4] + p2[6] ? 0.009 p2[4] + p2[6] + 0.057 v ? refhi = 3.2 x bandgap not allowed ? reflo = v dd/2 - bandgap not allowed ? reflo = bandgap not allowed ? reflo = 2 x bandgap - p2[6] (p2[6] = 0.5 v) not allowed ? reflo = p2[4] ? bandgap (p2[4] = v dd/2 ) not allowed ? reflo = p2[4]-p2[6] (p2[4] = v dd/2 , p2[6] = 0.5 v) p2[4] ? p2[6] ? 0.048 p2[4] ? p2[6] + 0.022 p2[4] ? p2[6] + 0.092 v table 10-12. dc analog psoc block specifications symbol description min typ max units notes r ct resistor unit value (continuous time) ? 12.2 ? k c sc capacitor unit value (switched capacitor) ? 80 ? ff note 13. agnd tolerance includes the offsets of the local buffer in the psoc block. bandgap voltage is 1.3 v 0.02 v . 14. avoid using p2[4] for digital signaling when using an analog re source that depends on the analog reference. some coupling of the digital signal may appear on the agnd. [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 29 of 51 10.3.9 dc por and lvd specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v or 3.3 v at 25 c and are for design guidance only. note the bits porlev and vm in the following table refer to bits in the vlt_cr register. see the psoc technical reference manual for more information on the vlt_cr register. table 10-13. dc por and lvd specifications symbol description min typ max units notes v ppor0r v ppor1r v ppor2r v dd value for ppor trip (positive ramp) porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? 2.91 4.39 4.55 ? v v v v ppor0 v ppor1 v ppor2 v dd value for ppor trip (negative ramp) porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? 2.82 4.39 4.55 ? v v v v ph0 v ph1 v ph2 ppor hysteresis porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? ? ? 92 0 0 ? ? ? mv mv mv v lvd0 v lvd1 v lvd2 v lvd3 v lvd4 v lvd5 v lvd6 v lvd7 v dd value for lvd trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.86 2.96 3.07 3.92 4.39 4.55 4.63 4.72 2.92 3.02 3.13 4.00 4.48 4.64 4.73 4.81 2.98 [15] 3.08 3.20 4.08 4.57 4.74 [16] 4.82 4.91 v v v v v v v v notes 15. always greater than 50 mv above ppor (porlev = 00) for falling supply. 16. always greater than 50 mv above ppor (porlev = 10) for falling supply. [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 30 of 51 10.3.10 dc programming specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 10-14. dc programming specifications symbol description min typ max units notes i ddp supply current during programming or verify ? 15 30 ma v ilp input low voltage during programming or verify ? ? 0.8 v v ihp input high voltage during programming or verify 2.1 ? ? v i ilp input current when apply ing vilp to p1[0] or p1[1] during programming or verify ? ? 0.2 ma driving internal pull-down resistor. i ihp input current when applying vihp to p1[0] or p1[1] during programming or verify ? ? 1.5 ma driving internal pull-down resistor. v olv output low voltage during programming or verify ? ? v ss + 0.75 v v ohv output high voltage during programming or verify v dd ? 1.0 ? v dd v flash enpb flash endurance (per block) [17] 50,000 ? ? ? erase/write cycles per block. flash ent flash endurance (total) [18] 1,800,000 ? ? ? erase/write cycles. flash dr flash data retention 10 ? ? years notes 17. the 50,000 cycle flash endurance per block will only be guaranteed if the flash is operating within one voltage range. volta ge ranges are 3.0 v to 3.6 v and 4.75 v to 5.25 v. 18. a maximum of 36 x 50,000 block endurance cycles is allowed. this may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cyc les each (to limit the total number of cycles to 36x50,000 a nd that no single block ever sees more than 50,000 cycles). for the full industrial range, the user must employ a temperatur e sensor user module (flashtemp) and feed the result to the tem perature argument before writing. refer to the flash apis application note an2015 at http://www.cypress.com under application notes for more information. [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 31 of 51 10.4 ac electrical characteristics 10.4.1 ac chip-level specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 10-15. ac chip-level specifications symbol description min typ max units notes f imo245v internal main oscillator frequency for 24 mhz (5 v) 23.04 24 24.96 [19,20] mhz trimmed for 5 v operation using factory trim values. f imo243v internal main oscillator frequency for 24 mhz (3.3 v) 22.08 24 25.92 [20,21] mhz trimmed for 3.3 v operation using factory trim values. f imousb5v internal main oscillator frequency with usb (5 v) frequency locking enabled and usb traffic present. 23.94 24 24.06 [20] mhz ?10 c t a 85 c 4.35 v dd 5.15 f imousb3v internal main oscillator frequency with usb (3.3 v) frequency locking enabled and usb traffic present. 23.94 24 24.06 [20] mhz ?0 c t a 70 c 3.15 v dd 3.45 f imo6 internal main oscillator frequency for 6 mhz 5.5 6 6.5 [19,20,21] mhz trimmed for 5 v or 3.3 v operation using factory trim values. see the figure on page 19. slimo mode = 1. f cpu1 cpu frequency (5 v nominal) 0.090 24 24.96 [19,20] mhz f cpu2 cpu frequency (3.3 v nominal) 0.086 12 12.96 [20,21] mhz f blk5 digital psoc block frequency (5 v nominal) 0 48 49.92 [19,20,22] mhz refer to the ac digital block specifications. f blk3 digital psoc block frequency (3.3 v nominal) 0 24 25.92 [20,22] mhz f 32k1 internal low speed oscillator frequency 15 32 64 khz f 32k_u internal low speed oscillator untrimmed frequency 5 ? ? khz after a reset and before the m8c starts to run, the ilo is not trimmed. see the system resets section of the psoc technical reference manual for details on timing this jitter32k 32 khz period jitter ? 100 ns t xrst external reset pulse width 10 ? ? s dc24m 24 mhz duty cycle 40 50 60 % dc ilo internal low speed oscillator duty cycle 20 50 80 % step24m 24 mhz trim step size ? 50 ? khz fout48m 48 mhz output frequency 46.08 48.0 49.92 [19,21] mhz trimmed. utilizing factory trim values. jitter24m1 24 mhz period jitter (imo) peak-to-peak ? 300 ps f max maximum frequency of signal on row input or row output. ? ? 12.96 mhz sr power_up power supply slew rate ? ? 250 v/ms v dd slew rate during power up. t powerup time from end of por to cpu executing code ? 16 100 ms power up from 0 v. see the system resets section of the psoc technical reference manual . [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 32 of 51 figure 10-2. 24 mhz period jitter (imo) ti ming diagram 10.4.2 ac general-purpose i/o specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. figure 10-3. gpio timing diagram 10.4.3 ac full-speed usb specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?10 c t a 85 c, or 3.0 v to 3.6 v and ?10 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. jitter24m1 f 24m notes 19. 4.75 v < v dd < 5.25 v. 20. accuracy derived from internal main oscillator with appropriate trim for v dd range. 21. 3.0 v < v dd < 3.6 v. see application note an2012 ?adjusting psoc microcontroller trims for dual voltage-ra nge operation? for information on trimming for operation at 3.3 v. 22. see the individual user module data sheets for information on maximum frequencies for user modules table 10-16. ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 12 mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf 3 ? 18 ns v dd = 4.5 to 5.25 v, 10% - 90% tfallf fall time, normal strong mode, cload = 50 pf 2 ? 18 ns v dd = 4.5 to 5.25 v, 10% - 90% trises rise time, slow strong mode, cload = 50 pf 10 27 ? ns v dd = 3 to 5.25 v, 10% - 90% tfalls fall time, slow strong mode, cload = 50 pf 10 22 ? ns v dd = 3 to 5.25 v, 10% - 90% table 10-17. ac full-speed (12 mbps) usb specifications symbol description min typ max units notes t rfs transition rise time 4 ? 20 ns for 50 pf load. t fss transition fall time 4 ? 20 ns for 50 pf load. t rfmfs rise/fall time matching: (t r /t f )90 ? 111 % for 50 pf load. t dratefs full-speed data rate 12 ? 0.25% 12 12 + 0.25% mbps tfallf tfalls trisef trises 90% 10% gpio pin output voltage [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 33 of 51 10.4.4 ac operational amplifier specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temper ature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. settling times, slew rates, and gain bandwidth are based on the analog continuous time psoc block. power = high and opamp bias = high is not supported at 3.3 v . table 10-18. 5-v ac operational amplifier specifications symbol description min typ max units t roa rising settling time from 80% of v to 0.1% of v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 3.9 0.72 0.62 s s s t soa falling settling time from 20% of v to 0.1% of v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 5.9 0.92 0.72 s s s sr roa rising slew rate (20% to 80%)(10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.15 1.7 6.5 ? ? ? ? ? ? v/ s v/ s v/ s sr foa falling slew rate (20% to 80%)(10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.01 0.5 4.0 ? ? ? ? ? ? v/ s v/ s v/ s bw oa gain bandwidth product power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.75 3.1 5.4 ? ? ? ? ? ? mhz mhz mhz e noa noise at 1 khz (power = medium, opamp bias = high) ? 100 ? nv/rt-hz table 10-19. 3.3-v ac operational amplifier specifications symbol description min typ max units t roa rising settling time from 80% of v to 0.1% of v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high ? ? ? ? 3.92 0.72 s s t soa falling settling time from 20% of v to 0.1% of v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high ? ? ? ? 5.41 0.72 s s sr roa rising slew rate (20% to 80%)(10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high 0.31 2.7 ? ? ? ? v/ s v/ s sr foa falling slew rate (20% to 80%)(10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high 0.24 1.8 ? ? ? ? v/ s v/ s bw oa gain bandwidth product power = low, opamp bias = low power = medium, opamp bias = high 0.67 2.8 ? ? ? ? mhz mhz e noa noise at 1 khz (power = medium, opamp bias = high) ? 100 ? nv/rt-hz [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 34 of 51 when bypassed by a capacitor on p2[4], the noise of the analog gr ound signal distributed to each block is reduced by a factor o f up to 5 (14 db). this is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacit or. figure 10-4. typical agnd noise with p2[4] bypass at low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. at high frequencies, increased power level reduces the noise spectrum level. figure 10-5. typical opamp noise 100 1000 10000 0.001 0.01 0.1 1 10 100 fr eq ( khz ) dbv/rthz 0 0.01 0.1 1.0 10 10 100 1000 10000 0.001 0.01 0.1 1 10 100 freq (khz) nv/rthz ph_ bh ph_ bl pm_ bl pl _ bl [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 35 of 51 10.4.5 ac low-power comparator specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v at 25 c and are for design guidance only. 10.4.6 ac digital block specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 10-20. ac low power comparator specifications symbol description min typ max units notes t rlpc lpc response time ? ? 50 s 50 mv overdrive comparator reference set within v reflpc . table 10-21. ac digita l block specifications function description min typ max units notes timer capture pulse width 50 [23] ? ? ns maximum frequency, no capture ? ? 49.92 mhz 4.75 v < v dd < 5.25 v. maximum frequency, with capture ? ? 25.92 mhz counter enable pulse width 50 [23] ? ? ns maximum frequency, no enable input ? ? 49.92 mhz 4.75 v < v dd < 5.25 v. maximum frequency, enable input ? ? 25.92 mhz dead band kill pulse width: asynchronous restart mode 20 ? ? ns synchronous restart mode 50 [23] ? ? ns disable mode 50 [23] ? ? ns maximum frequency ? ? 49.92 mhz 4.75 v < v dd < 5.25 v. crcprs (prs mode) maximum input clock frequency ? ? 49.92 mhz 4.75 v < v dd < 5.25 v. crcprs (crc mode) maximum input clock frequency ? ? 24.6 mhz spim maximum input clock frequency ? ? 8.2 mhz maximum data rate at 4.1 mhz due to 2 overclocking. spis maximum input clock frequency ? ? 4.1 mhz width of ss_ negated between transmissions 50 [23] ? ? ns transmitter maximum input clock frequency ? ? 24.6 mhz maximum data rate at 3.08 mhz due to 8 overclocking. receiver maximum input clock frequency ? ? 24.6 mhz maximum data rate at 3.08 mhz due to 8 overclocking. note 23. 50 ns minimum input pulse width is based on the input synchronizers running at 24 mhz (42 ns nominal period). [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 36 of 51 10.4.7 ac external clock specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temper ature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. 10.4.8 ac analog output buffer specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temper ature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 10-22. ac external clock specifications symbol description min typ max units notes f oscext frequency for usb applications 23.94 24 24.06 mhz ? duty cycle 47 50 53 % ? power up to imo switch 150 ? ? s table 10-23. 5-v ac analog output buffer specifications symbol description min typ max units notes t rob rising settling time to 0.1%, 1 v step, 100 pf load power = low power = high ? ? ? ? 2.5 2.5 s s t sob falling settling time to 0.1%, 1 v step, 100 pf load power = low power = high ? ? ? ? 2.2 2.2 s s sr rob rising slew rate (20% to 80%), 1 v step, 100 pf load power = low power = high 0.65 0.65 ? ? ? ? v/ s v/ s sr fob falling slew rate (80% to 20%), 1 v step, 100 pf load power = low power = high 0.65 0.65 ? ? ? ? v/ s v/ s bw obss small signal bandwidth, 20mv pp , 3db bw, 100 pf load power = low power = high 0.8 0.8 ? ? ? ? mhz mhz bw obls large signal bandwidth, 1v pp , 3db bw, 100 pf load power = low power = high 300 300 ? ? ? ? khz khz table 10-24. 3.3-v ac analog output buffer specifications symbol description min typ max units notes t rob rising settling time to 0.1%, 1 v step, 100 pf load power = low power = high ? ? ? ? 3.8 3.8 s s t sob falling settling time to 0.1%, 1 v step, 100 pf load power = low power = high ? ? ? ? 2.6 2.6 s s sr rob rising slew rate (20% to 80%), 1 v step, 100 pf load power = low power = high 0.5 0.5 ? ? ? ? v/ s v/ s sr fob falling slew rate (80% to 20%), 1 v step, 100 pf load power = low power = high 0.5 0.5 ? ? ? ? v/ s v/ s bw obss small signal bandwidth, 20mv pp , 3db bw, 100 pf load power = low power = high 0.7 0.7 ? ? ? ? mhz mhz bw obls large signal bandwidth, 1v pp , 3db bw, 100 pf load power = low power = high 200 200 ? ? ? ? khz khz [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 37 of 51 10.4.9 ac programming specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 10-25. ac programming specifications symbol description min typ max units notes t rsclk rise time of sclk 1 ? 20 ns t fsclk fall time of sclk 1 ? 20 ns t ssclk data setup time to falling edge of sclk 40 ? ? ns t hsclk data hold time from falling edge of sclk 40 ? ? ns f sclk frequency of sclk 0 ? 8 mhz t eraseb flash erase time (block) ? 10 ? ms t write flash block write time ? 40 ? ms t dsclk data out delay from falling edge of sclk ? ? 45 ns v dd > 3.6 t dsclk3 data out delay from falling edge of sclk ? ? 50 ns 3.0 v dd 3.6 t eraseall flash erase time (bulk) ? 40 ? ms erase all blocks and protection fields at once t program_hot flash block erase + flash block write time ? ? 100 [24] ms 0c tj 100 c t program_col d flash block erase + flash block write time ? ? 200 [24] ms ?40c tj 0 c note 24. for the full industrial range, the user must employ a temper ature sensor user module (flash temp) and feed the result to the temperature argument before writing. refer to the flash apis application note an2015 at http://www.cypress.com under application notes for more information. [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 38 of 51 10.4.10 ac i 2 c specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. figure 10-6. definition for timing for fast/standard mode on the i 2 c bus table 10-26. ac characteristics of the i 2 c sda and scl pins for v dd symbol description standard mode fast mode units notes min max min max f scli2c scl clock frequency 0 100 0 400 khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ?0.6 ? s t lowi2c low period of the scl clock 4.7 ?1.3 ? s t highi2c high period of the scl clock 4.0 ?0.6 ? s t sustai2c setup time for a repeated start condition 4.7 ?0.6 ? s t hddati2c data hold time 0 ?0 ? s t sudati2c data setup time 250 ?100 [25] ?ns t sustoi2c setup time for stop condition 4.0 ?0.6 ? s t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ? s t spi2c pulse width of spikes are suppressed by the input filter. ? ? 0 50 ns sda scl s sr s p t bufi2c t spi2c t hdstai2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c note 25. a fast-mode i2c-bus device can be used in a standard-mode i2c-bus system, but the requirement t su;dat ? 250 ns must then be met. this automatically is the case if the device does not stretch the low period of the scl signal . if such device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i2 c-bus specification) before the scl line is released. [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 39 of 51 11. packaging dimensions this section illustrates the package specification for the cy8c24 x94 psoc devices, along with the thermal impedance for the pac kage and solder reflow peak temperatures. important note emulation tools may require a larger area on the target pcb than the chip's footprint. for a detailed description of the emulation tools' dimensions, refer to the emulator pod dimension drawings at http://www.cypress .com/design/mr10161 . figure 11-1. 56-pin (7x7x0.6 mm) qfn 3. package weight: 0.0928 grams 1. hatch area is solderable exposed pad notes: 2. based on ref jedec # mo-220 4. all dimensions are in millimeters side view top view bottom view pad exposed solderable 001-58740 ** [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 40 of 51 figure 11-2. 56-pin (8x8 mm) qfn figure 11-3. 56-pin qfn (8 x 8 x 0.9 mm) - sawn top view 0.80[0.031] 7.70[0.303] 7.90[0.311] a c 1.00[0.039] max. n bottom view seating plane n 2 0.18[0.007] 0.50[0.020] 1 1 0.08[0.003] 0.50[0.020] 0.05[0.002] max. 2 side view (4x) c 0.24[0.009] 0.20[0.008] ref. 0.80[0.031] max. pin1 id 0-12 6.45[0.254] 8.10[0.319] 7.80[0.307] 6.55[0.258] 0.45[0.018] 0.20[0.008] r. 8.10[0.319] 7.90[0.311] 7.80[0.307] 7.70[0.303] dia. 0.28[0.011] 0.30[0.012] 6.55[0.258] 6.45[0.254] 0.60[0.024] 1. hatch area is solderable exposed metal. 2. reference jedec#: mo-220 4. all dimensions are in mm [min/max] notes : part # pb-free standard ly56a 5. package code description 3. package weight: 0.162g lf56a solderable exposed pad 4.5 5.2 001-12921 *a 001-53450 *b [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 41 of 51 figure 11-4. 68-pin (8x8 mm x 0.89 mm) qfn important note for information on the preferred dimensions for mounting qfn pa ckages, refer to application note, "application notes for surfac e mount assembly of amkor's microleadf rame (mlf) packages" available at http://www.amkor.com . pinned vias for thermal conduction are not required for the low-power psoc device. top view 1 2 3 a n 7.90[0.311] bottom view c side view plane seating 0-12 0.05[0.002] max 0.2[0.008] ref 0.9[0.035] max 0.70[0.028] max 0.08 c 0.18[0.007] 0.4 b.s.c. 0.20 r. 1 2 3 n 8.10[0.319] 7.70[0.303] 7.80[0.307] 7.90[0.311] 8.10[0.319] 7.70[0.303] 7.80[0.307] 0.28[0.011] 0.24[0.009] 0.60[0.023] 6.50[0.255] ref note : exposed pad dimension varies by leadframe cavity (paddle) si ze ? 5.69 pin1 id 2. reference jedec#: mo-220 4. all dimensions are in mm [min/max] notes : 1. hatch is solderable exposed pad. part # pb-free standard ly68 5. package code description 3. package weight: 0.17g lf68 solderable exposed pad 5.69 51-85214 *d [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 42 of 51 figure 11-5. 68-pin sawn qfn (8x8 mm x 0.90 mm) figure 11-6. 100-ball (6x6 mm) vfbga top view 0.200 ref pin 1 dot laser mark 1 8 3 4 3 5 5 1 5 2 6 8 1 1 7 0.08 c seating plane 0.05 max bottom view 1 0.4000.100 0.400 pitch 6 8 5 2 5 1 3 5 3 4 1 8 1 7 8.0000.100 8.0000.100 0.9000.100 6.40 ref 6.40 ref side view 0.200.05 5.70.10 pad exposed solderable 5.70.10 pin1 id r 0.20 001-09618 *c a 1 a1 corner 0.50 0.50 ?0.300.05(100x) ?0.15 m c a b ?0.05 m c b a 0.15(4x) 0.210.05 1.00 max c seating plane 0.45 ref. 0.10 c 0.08 c a1 corner top view bottom view 2 3 4 4.50 4.50 b c d e f g h 65 46 5 23 1 6.000.10 6.000.10 a 6.000.10 6.000.10 b 2.25 2.25 0.21 ref. j reference jedec mo-195c pkg. weight: tbd (new pkg.) 7 8 9 10 78910 k g k j h d f e c b a 51-85209 *c [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 43 of 51 figure 11-7. 100-pin (14x14 x 1.4 mm) tqfp 11.1 thermal impedance 11.2 solder reflow peak temperature following is the minimum solder reflow peak temperature to achieve good solderability. package typical ja [26] 56-pin qfn [27] 12.93 c/w 68-pin qfn [27] 13.05 c/w 100-ball vfbga 65 c/w 100-pin tqfp 51 c/w package minimum peak temperature [28] maximum peak temperature 56-pin qfn 240 c 260 c 68-pin qfn 240 c 260 c 100-ball vfbga 240 c 260 c 100-pin tqfp 240 c 260 c 51-85048 *d notes 26. t j = t a + power x ja 27. to achieve the thermal impedance specified for the qfn package,refer to "application notes for surface mount assembly of amk or's microleadframe (mlf) packages" available at http://www.amkor.com . 28. higher temperatures may be required based on the solder me lting point. typical temperatures for solder are 220 5 o c with sn-pb or 245 5 o c with sn-ag-cu paste. refer to the solder manufacturer specifications [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 44 of 51 12. development tool selection 12.1 software 12.1.1 psoc designer at the core of the psoc development software suite is psoc designer, used to generate psoc firmware applications. psoc designer is available free of charge at http://www.cypress.com and includes a free c compiler. 12.1.2 psoc programmer flexible enough to be used on the bench in development, yet suitable for factory progra mming, psoc programmer works either as a standalone programming application or it can operate directly from psoc designer. psoc programmer software is compatible with both psoc ice-cube in-circuit emulator and psoc miniprog. psoc programmer is available free of charge at http://www.cypress.com. 12.2 development kits all development kits can be purchased from the cypress online store . 12.2.1 cy3215-dk basic development kit the cy3215-dk is for prototyping and development with psoc designer. this kit supports in-circuit emulation, and the software interface enables you to run, halt, and single step the processor, and view the content of specific memory locations. advance emulation features also supported through psoc designer. the kit includes: psoc designer software cd ice-cube in-circuit emulator ice flex-pod for cy8c29x66 family cat-5 adapter mini-eval programming board 110 ~ 240 v power supply, euro-plug adapter imagecraft c compiler (registration required) issp cable usb 2.0 cable and blue cat-5 cable two cy8c29466-24pxi 28-pdip chip samples 12.3 evaluation tools all evaluation tools can be purchased from the cypress online store. 12.3.1 cy3210-miniprog1 the cy3210-miniprog1 kit enables you to program psoc devices via the miniprog1 programming unit. the miniprog is a small, compact prototyping prog rammer that connects to the pc via a provided usb 2.0 cable. the kit includes: miniprog programming unit minieval socket programming and evaluation board 28-pin cy8c29466-24pxi pdip psoc device sample 28-pin cy8c27443-24pxi pdip psoc device sample psoc designer software cd getting started guide usb 2.0 cable 12.3.2 cy3210-psoceval1 the cy3210-psoceval1 kit features an evaluation board and the miniprog1 programming unit. the evaluation board includes an lcd module, potentiomete r, leds, and plenty of bread- boarding space to meet all of your evaluation needs. the kit includes: evaluation board with lcd module miniprog programming unit 28-pin cy8c29466-24pxi pdip psoc device sample (2) psoc designer software cd getting started guide usb 2.0 cable 12.3.3 cy3214-psocevalusb the cy3214-psocevalusb evaluation kit features a devel- opment board for the cy8c24794-24lfxi psoc device. the board supports both usb and capacitive sensing development and debugging support. this evaluation board also includes an lcd module, potentiometer, leds, an enunciator and plenty of breadboarding space to meet all of your evaluation needs. the kit includes: psocevalusb board lcd module miniprog programming unit mini usb cable psoc designer and example projects cd getting started guide wire pack [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 45 of 51 12.4 device programmers all device programmers can be purchased from the cypress online store . 12.4.1 cy3216 modular programmer the cy3216 modular programmer kit features a modular programmer and the miniprog1 programming unit. the modular programmer includes three programming module cards and supports multiple cypress products. the kit includes: modular programmer base three programming module cards miniprog programming unit psoc designer software cd getting started guide usb 2.0 cable 12.4.2 cy3207issp in-system serial programmer (issp) the cy3207issp is a production programmer. it includes protection circuitry and an industrial case that is more robust than the miniprog in a production-programming environment. note : cy3207issp needs special software and is not compatible with psoc programmer. the kit includes: cy3207 programmer unit psoc issp software cd 110 ~ 240 v power supply, euro-plug adapter usb 2.0 cable 12.5 accessories (emulation and programming) table 12-1. emulation and programming accessories part # pin package flex-pod kit [29] foot kit [30] adapter [31] cy8c24794-24lfxi 56-pin qfn cy3250-24x94qfn cy 3250-56qfn-fk adapters can be found at http://www.emulation.com . cy8c24894-24lfxi 56-pin qfn cy3250-24x94qfn cy3250-56qfn-fk cy8c24794-24lqxi 56-pin qfn cy3250-24x94qfn none notes 29. flex-pod kit includes a practice flex-pod and a practice pcb, in addition to two flex-pods. 30. foot kit includes surface mount feet that are soldered to the target pcb. 31. programming adapter converts non-dip package to dip footprin t. specific details and ordering information for each of the ada pters are found at http://www.emulation.com. [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 46 of 51 13. ordering information note for die sales information, contact a local cypress sales office or field applications engineer (fae). table 13-1. cy8c24x94 psoc device?s key features and ordering information package ordering code flash (bytes) sram (bytes) temperature range digital blocks analog blocks digital i/o pins analog inputs analog outputs xres pin 100-pin ocd tqfp [32] CY8C24094-24AXI 16k 1k ?40 c to +85 c 4 6 56 48 2 yes 100-ball ocd (6x6 mm) vfbga [32] cy8c24094-24bvxi 16k 1k ?40 c to +85 c 4 6 56 48 2 yes 68-pin qfn (sawn) cy8c24094-24ltxi 16k 1k ?40 c to +85 c 4 6 56 48 2 yes 68-pin qfn (sawn) (tape and reel) cy8c24094-24ltxit 16k 1k ?40 c to +85 c 4 6 56 48 2 yes 56-pin (8x8 mm) qfn cy8c24794-24lfxi 16k 1k ?40 c to +85 c 4 6 50 48 2 no 56-pin (8x8 mm) qfn (tape and reel) cy8c24794-24lfxit 16k 1k ?40 c to +85 c 4 6 50 48 2 no 56-pin (8x8 mm) qfn (sawn) cy8c24794-24ltxi 16k 1k ?40 c to +85 c 4 6 50 48 2 no 56-pin (8x8 mm) qfn (sawn) (tape and reel) cy8c24794-24ltxit 16k 1k ?40 c to +85 c 4 6 50 48 2 no 56-pin (8x8 mm) qfn cy8c24894-24lfxi 16k 1k ?40 c to +85 c 4 6 49 47 2 yes 56-pin (8x8 mm) qfn (tape and reel) cy8c24894-24lfxit 16k 1k ?40 c to +85 c 4 6 49 47 2 yes 56-pin (8x8 mm) qfn (sawn) cy8c24894-24ltxi 16k 1k ?40 c to +85 c 4 6 49 47 2 yes 56-pin (8x8 mm) qfn (sawn) (tape and reel) cy8c24894-24ltxit 16k 1k ?40 c to +85 c 4 6 49 47 2 yes 100-ball (6x6 mm) vfbga cy8c24994-24bvxi 16k 1k ?40 c to +85 c 4 6 56 48 2 yes 68-pin qfn (sawn) cy8c24994-24ltxi 16k 1k ?40 c to +85 c 4 6 56 48 2 yes 68-pin qfn (sawn) (tape and reel) cy8c24994-24ltxit 16k 1k ?40 c to +85 c 4 6 56 48 2 yes notes 32. this part may be used for in-circuit debugging. it is not available for production [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 47 of 51 13.1 ordering code definitions cy package type: px = pdip pb-free sx = soic pb-free pvx = ssop pb-free lfx/lkx/lqx/ltx = qfn pb-free ax = tqfp pb-free bvx = vfbga pb-free speed: 24 mhz part number family code technology code: c = cmos marketing code: 8 = psoc company id: cy = cypress 8 c 24 xxx- sp xx thermal rating: c = commercial i = industrial e = extended [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 48 of 51 14. document conventions 14.1 acronyms used the following table lists the acronyms that are used in this document. 14.2 units of measure 14.3 numeric naming hexadecimal numbers are represented with all letters in uppercase with an appended lowercas e ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? prefix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, ?01010100b? or ?01000011b?). numbers not indicat ed by an ?h? or ?b? are decimal. acronym description ac alternating current adc analog-to-digital converter api application programming interface cpu central processing unit ct continuous time dac digital-to-analog converter dc direct current eco external crystal oscillator eeprom electrically erasable programmable read-only memory fsr full scale range gpio general purpose i/o gui graphical user interface hbm human body model ice in-circuit emulator ilo internal low speed oscillator imo internal main oscillator i/o input/output ipor imprecise power on reset lsb least-significant bit lvd low voltage detect msb most-significant bit pc program counter pll phase-locked loop por power on reset ppor precision power on reset psoc? programmable system-on-chip? pwm pulse width modulator sc switched capacitor sram static random access memory table 14-1. units of measure symbol unit of measure c degree celsius db decibels ff femtofarad hz hertz kb 1024 bytes kbit 1024 bits khz kilohertz k kilohm mhz megahertz m megaohm a microampere f microfarad h microhenry s microsecond v microvolts vrms microvolts root-mean-square w microwatts ma milliampere ms millisecond mv millivolts na nanoampere ns nanosecond nv nanovolts ohm pa picoampere pf picofarad pp peak-to-peak ppm parts per million ps picosecond sps samples per second sigma: one standard deviation v volts [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 49 of 51 15. document history page document title: cy8c24094, cy 8c24794, cy8c24894, cy8c24994 psoc ? programmable system-on-chip document number: 38-12018 rev. ecn no. submission date orig. of change description of change ** 133189 01.27.2004 nwj new silicon and new document ? advance data sheet. *a 251672 see ecn sfv first preliminary data sheet. changed title to encompass only the cy8c24794 because the cy8c24494 and cy8c24694 are not being offered by cypress. *b 289742 see ecn hmt add standard ds items from sfv memo. add analog input mux on pinouts. 2 macs. change 512 bytes of sram to 1k. add dimension key to package. remove hapi. update diagrams, registers and specs. *c 335236 see ecn hmt add cy logo. update cy copyright. update new cy.com urls. re-add issp programming pinout notation. add reflow temp. table. update features (mac, oscillator, and voltage range), registers (int_clr2/msk2, second mac), and specs. (rext, imo, analog output buffer...). *d 344318 see ecn hmt add new color and logo. expand analog arch. diagram. fix i/o #. update electrical specifications. *e 346774 see ecn hmt add usb temperature specifications. make data sheet final. *f 349566 see ecn hmt remove usb logo. add url to preferred dimensions for mounting mlf packages. *g 393164 see ecn hmt add new device, cy8c24894 56-pin mlf with xres pin. add fimousb3v char. to specs. upgrade to cy perform logo and update corporate address and copyright. *h 469243 see ecn hmt add issp note to pinout tables. update typical and recommended storage temperature per industrial specs. update low output level maximum i/ol budget. add fls_pr1 to register map bank 1 for users to specify which flash bank should be used for srom operations. add two new devices for a 68-pin qfn and 100-ball vfbga under rpns: cy8c24094 and cy8c24994. add two packages for 68-pin qfn. add ocd non-production pinouts and package diagrams. update cy branding and qfn conv ention. add new dev. tool section. update copyright and trademarks. *i 561158 see ecn hmt add low power comparator (lpc) ac/dc electrical spec. tables. add cy8c20x34 to psoc device characteristics table. add detailed dimensions to 56-pin qfn package diagram and update revision. secure one package diagram/manufacturing per qfn. update em ulation pod/feet kit part numbers. fix pinout type-o per testtrack. *j 728238 see ecn hmt add capsense snr requirement reference. update figure standards. update technical training paragraphs. add qfn package clarifications and dimensions. update ecn-ed amkor dimensioned qfn package diagram revisions. reword snr reference. add new 56-pin qfn spec. *k 2552459 08/14/08 azie/pyrs add footnote on agnd descriptions to avoid using p2[4] for digital signaling as it may add noise to agnd. remove refer ence to cmp_go_en1 in map bank 1 table on address 65; this register has no functionality on 24xxx. add footnote on die sales. add description 'optional external clock input? on p1[4] to match description of p1[4]. *l 2616550 12/05/08 ogne/pyrs updated programmable pin configuration detail. changed title from psoc? mixed-signal array to psoc? programmable system-on-chip? *m 2657956 02/11/09 dpt/pyrs added package diagram 001-09618 and updated ordering information table [+] feedback
cy8c24094, cy8c24794 cy8c24894, cy8c24994 document number: 38-12018 rev. *v page 50 of 51 *n 2708135 05/18/2009 brw added note in the pin information section on page 8. removed reference to hi-tech lite compiler in the section development tools selection on page 42. *o 2718162 06/11/2009 dpt added 56-pin qfn (sawn) package diagram and updated ordering information *p 2762161 09/10/2009 rlrm updated the following parameters: dc ilo, f32k_u, f imo6 , t powerup , t erase_all , t program_hot , and t program_cold. added sr power_up parameter in ac specs table . *q 2768530 09/24/09 rlrm ordering information table: changed xres pin value for cy8c24894-24ltxi and cy8c24894-24ltxit to ?yes?. *r 2817938 11/30/09 kris ordering information : updated cy8c24894-24ltxi and cy8c24894-24ltxit parts as sawn and updated the digital i/o and analog pin values added contents page. updated 68 qfn package diagram (51-85124) *s 2846641 1/12/10 rlrm added package diagram 001-58740 and updated development tools section. *t 2867363 01/27/10 anup modified note 9 to remove voltage range 2.4 v to 3.0 v *u 2901653 03/30/2010 njf updated cypress website links added t xrst , dc24m, t baketemp and t baketime parameters removed reference to 2.4 v removed sections ?third party tools? ?build a psoc emulator into your board? updated package diagrams removed inactive parts from ordering information table. *v 2938528 05/28/2010 vmad updated content to match current st yle guide and datasheet template. no technical updates document title: cy8c24094, cy 8c24794, cy8c24894, cy8c24994 psoc ? programmable system-on-chip document number: 38-12018 [+] feedback
document number: 38-12018 rev. *v revised may 27, 2010 page 51 of 51 psoc designer? is a trademark and psoc? is a registered trademark of cypress semiconductor corp. all other trademarks or regist ered trademarks referenced herein are property of the respective corporations. cy8c24094, cy8c24794 cy8c24894, cy8c24994 ? cypress semiconductor corporation, 2004-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. 16. sales, solutions , and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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